Memory system and method for two step write operations

A memory system, comprising:

• a communication channel coupled to a master memory device and coupled to a slave memory device;
• the master memory device configured to generate control information and associated data information including a plurality of write commands with associated write information for each write command to the slave memory device followed by any operation code other than a read or write command to the slave memory device and then followed by a read command to the slave memory device;
• and
• the slave memory device configured to receive the control information and associated data information in a same order as generated by the master memory device and to process the read command delayed according to the operation code other than a read or write command to the slave memory device prior to completing the processing of at least one of the plurality of write commands without causing a column resource conflict at a memory core of the slave memory device.

A method of operating a memory system with a master memory device coupled to a slave memory device, the method comprising:

• generating with the master memory device control information and associated data information including a plurality of write commands with associated write information for each write command to the slave memory device followed by any operation code other than a read or write command to the slave memory device and then followed by a read command to the slave memory device;
• transporting the associated write information of at least one of the plurality of write commands into a write data buffer;
• processing the read command at the slave memory device;
• and
• completing the processing of at least one of the plurality of write commands at the slave memory device after processing the read command so as to avoid a column resource conflict at a memory core of the slave memory device.

A method of operating a memory system with a master memory device coupled to a slave memory device, the method comprising:

• generating with the master memory device control information and associated data information including a plurality of write commands with associated write information for each write command to the slave memory device followed by any operation code other than a read or write command to the slave memory device and then followed by a read command to the slave memory device;
• receiving the control information and associated data information in the slave memory device in a same order as generated by the master memory device;
• processing the read command at the slave memory device;
• and
• completing the processing of at least one of the plurality of write commands at the slave memory device after processing the read command delayed according to the operation code other than a read or write command to the slave memory device so as to avoid a column resource conflict at a memory core of the slave memory device.