Data management method for memory device

A method of managing data stored in a memory apparatus having an irreversibly writeable memory, said method comprising:

• obtaining a logical address;
• calculating a physical address in the irreversibly writeable memory from the logical address using a fixed mathematical relation;
• providing a block correlation table that includes a plurality of block addresses of unusable block portions in the irreversibly writeable memory and a plurality of addresses of substitute block portions in the irreversibly writeable memory each associated with a specific one of the plurality of block addresses, the plurality of block addresses of the block correlation table being sorted in an ascending order or in a descending order;
• comparing the physical address with each of the plurality of block addresses until either the physical address matches a current one of the plurality of block addresses, the physical address is smaller than or equal to the current one of the plurality of block addresses when the plurality of block addresses are sorted in the ascending order, or the physical address is greater than or equal to the current one of the plurality of block addresses when the plurality of block addresses are sorted in the descending order;
• and
• referencing the irreversibly writeable memory using the physical address when the physical address does not match any of the block addresses in the block correlation table and referencing the irreversibly writeable memory using the address of its associated substitute block portion when the physical address matches one of the block addresses in the block correlation table.

A method of managing data stored in a memory apparatus having an irreversibly writeable memory, said method comprising:

• obtaining a logical address;
• calculating a physical address in the irreversibly writeable memory using the mathematical relation:
• Nphy=(Nlog×Nmul)+Nbase,
• where Nphy is the physical address, Nlog is the logical address, Nmul is a multiplier value, and Nbase is a base value;
• and
• referencing the irreversibly writeable memory using the physical address.

A method of managing data stored in a memory apparatus having an irreversibly writeable memory, the irreversibly writeable memory including a plurality of cells, said method comprising:

• obtaining a logical address;
• calculating a physical address in the irreversibly writeable memory using the mathematical relation:
• Nphy=((Nlog×Nmul)+Nbase)% Nblknum,
• and calculating a cell number in the irreversibly writeable memory using the mathematical relation:
• Nphy=((Nlog×Nmul)+Nbase)/Nblknum,
• where Nphy is the physical address, Nlog is the logical address, Nmul is a multiplier value, Nbase is a base value, Nblknum is a designated value per cell, and % defines a remainder value after division by Nblknum;
• and
• referencing the irreversibly writeable memory using the cell number and the physical address.

A memory apparatus, comprising:

• an irreversibly writeable memory;
• a data processor operable to obtain a logical address and to calculate a physical address in the irreversibly writeable memory from the logical address using a fixed mathematical relation;
• and
• a table storage unit operable to store a block correlation table that includes block addresses of only unusable block portions in said irreversibly writeable memory and addresses of substitute block portions in said irreversibly writeable memory each associated with a specific one of the block addresses of the unusable block portions;
• said data processor being further operable to compare the physical address with the block address in the block correlation table, to reference the irreversibly writeable memory using the physical address when the physical address does not match any of the block addresses in the block correlation table, and to reference the irreversibly writeable memory using the address of the associated substitute block portion when the physical address matches one of the block addresses in the block correlation table.

A memory apparatus comprising:

• an irreversibly writeable memory;
• and a data processor operable to obtain a logical address, to calculate a physical address in the irreversibly writeable memory using the mathematical relation:
• Nphy=(Nlog×Nmul)+Nbase,
• where Nphy is the physical address, Nlog is the logical address, Nmul is a multiplier value, and Nbase is a base value, and to reference the irreversibly writeable memory using the physical address.

A memory apparatus comprising:

• an irreversibly writeable memory that includes a plurality of cells;
• and
• a data processor operable to obtain a logical address, to calculate a physical address in the irreversibly writeable memory using the mathematical relation:
• Nphy=((Nlog×Nmul)+Nbase)% Nblknum,
• and to calculate a cell number in the irreversibly writeable memory using the mathematical relation:
• Nphy=((Nlog×Nmul)+Nbase)/Nblknum,
• where Nphy is the physical address, Nlog is the logical address, Nmul is a multiplier value, Nbase is a base value, Nblknum is a designated value per cell, and % defines a remainder value after division by Nblknum, and to reference the irreversibly writeable memory using the cell number and the physical address.

A memory apparatus comprising:

• an irreversibly writeable memory;
• a table storage unit operable to store a block correlation table that includes a plurality of block addresses of unusable block portions in said irreversibly writeable memory and a plurality of addresses of substitute block portions in said irreversibly writeable memory each associated with a specific one of the plurality of block addresses, the plurality of block addresses of the block correlation table being sorted in an ascending order or in a descending order;
• and
• a data processor operable to obtain a logical address, to calculate a physical address in the irreversibly writeable memory from the logical address using a fixed mathematical relation, to compare the physical address with each of the plurality of block addresses until either the physical address matches a current one of the plurality of block addresses, the physical address is smaller than or equal to the current one of the plurality of block addresses when the plurality of block addresses are sorted in the ascending order, or the physical address is greater than or equal to the current one of the plurality of block addresses when the plurality of block addresses are sorted in the descending order, to reference the irreversibly writeable memory using the physical address when the physical address does not match any of the block addresses in the block correlation table, and to reference the irreversibly writeable memory using the address of the associated substitute block portion when the physical address matches one of the block addresses in the block correlation table.

A system, comprising:

• a memory apparatus including:
• an irreversibly writeable memory, and
• a table storage unit operable to store a block correlation table that includes block addresses of only unusable block portions in said irreversibly writeable memory and addresses of substitute block portions in said irreversibly writeable memory each associated with a specific one of the block addresses of the unusable block portions;
• and
• a host apparatus operable to obtain a logical address and to calculate a physical address in the irreversibly writeable memory from the logical address using a fixed mathematical relation;
• one of said memory apparatus and said host apparatus being operable to reference the block correlation table and to compare the physical address with the block addresses in the block correlation table;
• said memory apparatus being operable to reference the irreversibly writeable memory using the physical address when the physical address does not match any of the block addresses in the block correlation table and to reference the irreversibly writeable memory using the address of its associated substitute block portion when the physical address matches one of the block addresses in the block correlation table.

A system, comprising:

• a memory apparatus including an irreversibly writeable memory;
• and
• a host apparatus operable to obtain a logical address and to calculate a physical address in the irreversibly writeable memory from the logical address using the mathematical relation:
• Nphy=(Nlog×Nmul)+Nbase,
• where Nphy is the physical address, Nlog is the logical address, Nmul is a multiplier value, and Nbase is a base value;
• said memory apparatus being operable to reference the irreversibly writeable memory using the physical address.

A system, comprising:

• a memory apparatus including an irreversibly writeable memory that includes a plurality of cells;
• and
• a host apparatus operable to obtain a logical address, and to calculate a physical address in the irreversibly writeable memory using the mathematical relation:
• Nphy=((Nlog×Nmul)+Nbase)% Nblknum,
• and to calculate a cell number in the irreversibly writeable memory using the mathematical relation:
• Nphy=((Nlog×Nmul)+Nbase)% Nblknum,
• where Nphy is the physical address, Nlog is the logical address, Nmul is a multiplier value, Nbase is a base value, Nblknum is a designated value per cell, and % defines a remainder value after division by Nblknum;
• said memory apparatus being operable to reference the irreversibly writeable memory using the cell number and the physical address.

A system, comprising:

• a memory apparatus including:
• an irreversibly writeable memory, and
• a table storage unit operable to store a block correlation table that includes a plurality of block addresses of unusable block portions in said irreversibly writeable memory and a plurality of addresses of substitute block portions in said irreversibly writeable memory each associated with a specific one of the plurality of block addresses, the plurality of block addresses of the block correlation table being sorted in an ascending order or in a descending order;
• and
• a host apparatus operable to obtain a logical address and to calculate a physical address in the irreversibly writeable memory from the logical address using a fixed mathematical relation;
• one of said memory apparatus and said host apparatus being operable to compare the physical address with each of the plurality of block addresses until either the physical address matches a current one of the plurality of block addresses, the physical address is smaller than or equal to the current one of the plurality of block addresses when the plurality of block addresses are sorted in the ascending order, or the physical address is greater than or equal to the current one of the plurality of block addresses when the plurality of block addresses are sorted in the descending order;
• said memory apparatus being operable to reference the irreversibly writeable memory using the physical address.