Pre-stored vector interrupt handling system and method

In a system comprising a processor, a method for pre-stored vector interrupt handling, comprising the steps of:

• intercepting a processor's normal instruction fetch bus cycle;
• generating an interrupt identifier signal to the interrupt vector store;
• and
• delivering a pre-stored interrupt vector directly to the execution unit of the processor, said pre-stored interrupt vector dependent upon said interrupt identifier signal.

A system for handling interrupts in a processor-controlled device, said processor-controlled device comprising a processor executing a software program stored as a set of program instructions, the system comprising:

• an interrupt vector store;
• an interrupt controller connected to a plurality of interrupt request signals, said interrupt controller outputting a master interrupt signal;
• and
• a selector in a controlling arrangement with said interrupt vector store and with a memory storing program instructions being executed by the processor, said selector causing an execution unit of the processor to receive the next program instruction when the master interrupt signal is not asserted, and to receive an interrupt vector directly from the interrupt vector store when the master interrupt signal is asserted, the interrupt vector comprising a branch instruction op-code and address.

A method for handling interrupts in a processor-controlled device, said processor-controlled device comprising a processor executing a software program Stored as a set of program instructions, the method comprising:

• storing interrupt vectors in an interrupt vector store;
• connecting an interrupt controller to a plurality of interrupt request signals;
• outputting a master interrupt signal from the interrupt controller;
• causing the processor to receive the next program instruction when the master interrupt signal is not asserted;
• and
• causing an execution unit of the processor to receive an interrupt vector directly from the interrupt vector store when the master interrupt signal is asserted, the interrupt vector comprising a branch instruction op-code and address.