Method and apparatus for fast acknowledgement and efficient servicing of interrupt sources coupled to high latency paths

A method for acknowledging and servicing an interrupt issued to a processor of an intermediate node, the method comprising the steps of:

• generating a pulsed interrupt signal at an external device coupled to a high latency path;
• transporting the pulsed interrupt signal to an interrupt multiplexing device over a low latency path coupling the external device to the interrupt multiplexing device;
• asserting a status bit in response to detecting the pulsed interrupt signal at the interrupt multiplexing device;
• issuing a level sensitive interrupt (LSI) signal to the processor in response to each pulsed interrupt signal received at the interrupt multiplexing device, the LSI signal remaining asserted until the interrupt is acknowledged by the processor;
• and
• invoking an interrupt handler to service the issued interrupt;
• acknowledging the interrupt by by clearing the status bit in the interrupt multiplexing device.

Apparatus for acknowledging and servicing an interrupt issued to a processor of an intermediate node, the apparatus comprising:

• means for generating a pulsed interrupt signal at an external device coupled to a high latency path;
• means for transporting the pulsed interrupt signal to an interrupt multiplexing device over a low latency path coupling the external device to the interrupt multiplexing device;
• means for asserting a status bit in response to detecting the pulsed interrupt signal at the interrupt multiplexing device;
• means for issuing a level sensitive interrupt (LSI) signal to the processor in response to each pulsed interrupt signal received at the interrupt multiplexing device, the LSI signal remaining asserted until the interrupt is acknowledged by the processor;
• and
• means for invoking an interrupt handler to service the issued interrupt;
• means for acknowledging the interrupt by by clearing the status bit in the interrupt multiplexing device.

A computer readable medium containing executable program instructions for acknowledging and servicing an interrupt issued to a processor an intermediate node, the executable program instructions comprising program instructions for:

• generating a pulsed interrupt signal at an external device coupled to a high latency path;
• transporting the pulsed interrupt signal to an interrupt multiplexing device over a low latency path coupling the external device to the interrupt multiplexing device;
• asserting a status bit in response to detecting the pulsed interrupt signal at the interrupt multiplexing device;
• issuing a level sensitive interrupt (LSI) to the processor in response to each pulsed interrupt signal received at the interrupt multiplexing device, the LSI signal remaining asserted until the interrupt is acknowledged by the processor;
• and
• invoking an interrupt handler to service the issued interrupt;
• acknowledging the interrupt by by clearing the status bit in the interrupt multiplexing device.

Electromagnetic signals propagating on a computer network comprising,

• the electromagnetic signals carrying instructions for execution on a processor for:
• generating a pulsed interrupt signal at an external device coupled to a high latency path;
• transporting the pulsed interrupt signal to an interrupt multiplexing device over a low latency path coupling the external device to the interrupt multiplexing device;
• asserting a status bit in response to detecting the pulsed interrupt signal at the interrupt multiplexing device;
• issuing a level sensitive interrupt (LSI) to the processor in response to each pulsed interrupt signal received at the interrupt multiplexing device, the LSI signal remaining asserted until the interrupt is acknowledged by the processor;
• and
• invoking an interrupt handler to service the issued interrupt;
• acknowledging the interrupt by by clearing the status bit in the interrupt multiplexing device.

A method for acknowledging and servicing an interrupt issued to a processor, the method comprising:

• generating a pulsed interrupt signal at an external device;
• transporting the pulsed interrupt signal to an interrupt multiplexing device over a first low latency path that couples the external device to the interrupt multiplexing device;
• asserting a status bit in the interrupt multiplexing device corresponding to the interrupt in response to detecting the pulsed interrupt signal;
• issuing to the processor over a second low latency paths, in response to the pulsed interrupt signal, a level sensitive interrupt (LSI) signal, the LSI signal remaining asserted until the interrupt is acknowledged by the processor;
• reading the status bit over the second low latency path by an interrupt handler internal to the processor;
• and
• clearing the status bit in response to the reading of the status bit to effectively acknowledge the interrupt.

An apparatus for acknowledging and servicing an interrupt issued to a processor, the apparatus comprising:

• an external device generating a pulsed interrupt signal;
• a first low latency path that couples the external device to an interrupt multiplexing device for transporting the pulsed interrupt signal to the interrupt multiplexing device;
• a status bit in the interrupt multiplexing device corresponding to the asserted interrupt and set in response to detecting the pulsed interrupt signal;
• a second low latency path for issuing to the processor, in response to the pulsed interrupt signal, a level sensitive interrupt (LSI) signal, the LSI signal remaining asserted until acknowledged by the processor;
• an interrupt handler internal to the processor for reading and clearing the status bit over the second low latency path, whereby clearing the status bit effectively acknowledges the interrupt and causes the LSI signal to be deasserted.

An apparatus for acknowledging and servicing an interrupt issued to a processor, the apparatus comprising:

• means for generating a pulsed interrupt signal at an external device;
• means for transporting the pulsed interrupt signal to an interrupt multiplexing device over a first low latency path that couples the external device to the interrupt multiplexing device;
• means for asserting a status bit in the interrupt multiplexing device corresponding to the interrupt in response to detecting the pulsed interrupt signal;
• means for issuing to the processor over a second low latency path, in response to the pulsed interrupt signal, a level sensitive interrupt (LSI) signal, the LSI signal remaining asserted until the interrupt is acknowledged by the processor;
• means for reading the status bit over the second low latency path by an interrupt handler internal to the processor;
• and
• means for clearing the status bit in response to the reading of the status bit to effectively acknowledge the interrupt.

A computer readable media comprising, the computer readable media having instructions written thereon for execution on a processor for:

• generating a pulsed interrupt signal at an external device;
• transporting the pulsed interrupt signal to an interrupt multiplexing device over a first low latency path that couples the external device to the interrupt multiplexing device;
• asserting a status bit in the interrupt multiplexing device corresponding to the interrupt in response to detecting the pulsed interrupt signal;
• issuing to the processor over a second low latency path, in response to the pulsed interrupt signal, a level sensitive interrupt (LSI) signal, the LSI signal remaining asserted until the interrupt is acknowledged by the processor;
• reading the status bit over the second low latency path by an interrupt handler internal to the processor;
• and
• clearing the status bit in response to the reading of the status bit to effectively acknowledge the interrupt.

Electromagnetic signals propagating on a computer network comprising,

• the electromagnetic signals carrying instructions for execution on a processor for:
• generating a pulsed interrupt signal at an external device;
• transporting the pulsed interrupt signal to an interrupt multiplexing device over a first low latency path that couples the external device to the interrupt multiplexing device;
• asserting a status bit in the interrupt multiplexing device corresponding to the interrupt in response to detecting the pulsed interrupt signal;
• issuing to the processor over a second low latency path, in response to the pulsed interrupt signal, a level sensitive interrupt (LSI) signal, the LSI signal remaining asserted until the interrupt is acknowledged by the processor;
• reading the status bit over the second low latency path by an interrupt handler internal to the processor;
• and
• clearing the status bit in response to the reading of the status bit to effectively acknowledge the interrupt.