US 6,889,272 B1 · Parallel data bus with bit position encoded on the clock wire

Abstract

A system and method for transmitting parallel data from a source to a destination over a plurality of high speed serial lines operates reliably even in the presence of data skew. The high speed data transmission system includes a protocol generator, a de-skew circuit, and a plurality of high speed serial lines coupled between the protocol generator and the de-skew circuit. Respective serial representations of parallel data words are transmitted to the destination over a plurality of serial data lines, and a clock signal is transmitted to the destination over a clock line in parallel with the serial data lines. The clock signal has at least one data bit of each parallel data word encoded thereon. The de-skew circuit aligns regenerated parallel data words using the respective data bits encoded on the clock signal to eliminate skew among the data bits, and regenerates the parallel data from the aligned parallel data words.

Claims14

Dependent claims

A method of transmitting parallel data to a destination over a plurality of serial data lines, comprising the steps of:

segregating the parallel data into a plurality of parallel data words, each parallel data word comprising a plurality of data bits;
converting the plurality of parallel data words to respective serial representations of the data words;
transmitting the respective serial representations of the data words to the destination over the plurality of serial data lines;
transmitting a clock signal to the destination over a clock line in parallel with the plurality of serial data lines, the clock signal having at least one data bit of each parallel data word encoded thereon;
converting the transmitted serial representations of the data words to parallel form to regenerate the plurality of parallel data words;
aligning the regenerated parallel data words using the respective data bits encoded on the clock signal;
and
regenerating the parallel data from the aligned parallel data words.

5 more elements

A system for transmitting parallel data to a destination, comprising:

a protocol generator configured to (1) segregate the parallel data into a plurality of parallel data words, each parallel data word comprising a plurality of data bits, and (2) generate protocol data comprising at least one data bit of each parallel data word;
a plurality of parallel-to-serial converters configured to convert the plurality of parallel data words to respective serial data and convert the protocol data to a clock signal having the at least one data bit of each parallel data word encoded thereon;
a plurality of serial data lines configured to transmit the respective serial data to the destination;
a clock line configured to transmit the clock signal to the destination;
a plurality of serial-to-parallel converters configured to convert the respective serial data to parallel form to regenerate the plurality of parallel data words and convert at least a portion of the data encoded on the clock signal to parallel form to regenerate the protocol data;
and
a de-skew circuit configured to (1) align the regenerated parallel data words using the at least one data bit of each parallel data word included in the protocol data, and (2) regenerate the parallel data from the aligned parallel data words.

4 more elements

Dependencies are inferred from the claim text.

Parallel data bus with bit position encoded on the clock wire

Life of this patent

Parallel data bus with bit position encoded on the clock wire

Life of this patent

Abstract

Claims14