Multi-chip system having a continuous burst read mode of operation
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-Hyuk Chae, Heung-Soo Im
Life of this patent
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Abstract
Embodiments of the invention provide a multi-chip system that includes a first and a second semiconductor memory device. The memory devices are mounted in a single package. The multi-chip system has a continuous burst read mode of operation, in which a read operation can be successively carried out without latency even though an address region moves from the first semiconductor memory device to the second memory device.
Claims11
A synchronous semiconductor memory device that includes a burst read mode of operation having a plurality of internal burst cycles, comprising:
- a memory cell array that stores data information;
- an address generating circuit that operates synchronized with a clock signal and sequentially generates an internal address for the burst read mode of operation in response to an external address;
- a data read circuit that reads out burst data from the memory cell array based on a part of the internal address, the burst data being outputted during the respective internal burst cycles;
- a read control circuit that operates responsive to a read enable signal and controls a read operation of the data read circuit at a transition of either one of the external address and the internal address;
- a burst control circuit that operates responsive to a burst enable signal and generates a latch enable signal synchronized with the clock signal;
- a data register that latches the burst data read out through the read circuit in response to the latch enable signal and sequentially outputs the latched burst data in response to another part of the internal address;
- and
- a detection means that detects whether the internal address reaches a burst address set corresponding to the last one of the internal burst cycles and generates the burst enable signal and the read enable signal for controlling the burst control circuit and the read control circuit based on a detection result.
A multi-chip system that includes a burst read mode of operation having a plurality of internal burst cycles, comprising:
- a clock line that transfers a clock signal;
- a first bus that transfers control signals;
- a second bus that selectively transfers data and an address;
- a first semiconductor memory device that is connected to the clock line and the first bus;
- and
- a second semiconductor memory device that is connected to the clock line and the second bus,
- wherein each of the first and second semiconductor memory devices comprise
- a memory cell array that stores data information;
- an address generating circuit that operates synchronized with the clock signal and sequentially generates an internal address for the burst read mode of operation in response to an external address;
- a data read circuit that reads out burst data from the memory cell array based on a part of the internal address, the burst data being outputted during the respective internal burst cycles;
- a read control circuit that operates responsive to a read enable signal and controls a read operation of the data read circuit at a transition of either one of the external address and the internal address;
- a burst control circuit that operates responsive to a burst enable signal and generates a latch enable signal synchronized with the clock signal;
- a data register that latches the burst data read out through the read circuit in response to the latch enable signal and sequentially outputs the latched burst data in response to another part of the internal address;
- and
- detection means that detect whether the internal address reaches a burst address set corresponding to the last one of the internal burst cycles and generates the burst enable signal and the read enable signal for controlling the burst control circuit and the read control circuit based on a detection result.
Dependencies are inferred from the claim text.