Floating point adder
AssigneeIntel Corporation
InventorsAmaresh Pangal, Dinesh Somasekhar, Sriram R. Vangal, Yatin V. Hoskote
Life of this patent
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Abstract
A floating point adder circuit includes an exponent path and a mantissa path. The exponent path includes a comparator to compare two three-bit exponents. The two exponents are each incremented, and a resultant exponent is chosen from one of the two original exponents or one of the incremented exponents. The mantissa path includes an adder to add mantissas, and an adder bypass path to select one of the mantissas in lieu of performing an addition. The mantissa path also includes constant shifters that conditionally shift the mantissas right by thirty-two bit positions.
Claims40
A floating point adder circuit comprising:
- an exponent path to compare exponents of floating-point numbers having least significant bits with a weight of other than one, wherein the exponent path includes a comparator comprising:
- a first input node to accept a first three-bit exponent having a least significant bit with a weight of thirty-two,
- a second input node to accept a second three-bit exponent having a least significant bit with a weight of thirty-two, and
- a plurality of output nodes to signify whether the first exponent is larger, smaller, or equal to the second exponent;
- a mantissa path having a shifter to shift a mantissa of one of the floating-point numbers responsive to the exponent path, wherein the mantissa path comprises a constant shifter to conditionally shift a mantissa by thirty-two bits.
A floating point adder circuit comprising:
- an exponent path to compare exponents having least significant bits with a weight of other than one;
- wherein the exponent path includes a comparator to compare three bit exponents of two floating point numbers;
- and
- a mantissa path having a shifter to shift a mantissa of one of the floating point numbers, responsive to the exponent path, wherein the mantissa path includes a constant shifter to conditionally shift a mantissa of one of the two floating point numbers by thirty-two bits.
A method of floating point addition comprising:
- comparing an exponent of a first floating point number to an exponent of a second floating point number;
- if the exponent of the first floating point number is one greater than the exponent of the second floating point number, shifting a mantissa of the second floating point number thirty-two bit positions to the right;
- selecting the first exponent as a resultant exponent;
- and
- producing a resultant mantissa from a mantissa of the first floating point number and the shifted mantissa of the second floating point number.
A method, comprising:
- receiving two input floating-point numbers having input mantissas and having input exponents having a first base whose least significant bits have a first weight;
- converting the input exponents and the input mantissas to a second base whose least significant bit has a second weight greater than the first weight;
- comparing the converted exponents without adding or subtracting them;
- conditionally shifting the converted mantissas by a fixed amount in response to the comparing operation to produce intermediate mantissas.
An apparatus comprising
- input nodes to receive two input FP numbers, having input mantissas and having input exponents having a first base whose least significant bits have a first weight;
- an input converter to modify the input exponents to a second base whose least significant bit has a second weight greater than the first weight;
- a comparator to compare the converted exponents;
- a shifter responsive to the comparator to conditionally shift the converted mantissas by a fixed amount determined by the second weight, to produce intermediate mantissas.
Dependencies are inferred from the claim text.