Back to results
US 6,888,905 B1Granted
Low deviation index demodulation scheme
AssigneeMicrotune (San Diego), Inc.
InventorsJonathon Cheah, Jianping Pan, Le Luong
Life of this patent
Estimating the term…
Abstract
A wireless receiver e.g., a Bluetooth-compatible receiver or a receive chain in a Bluetooth-compatible transceiver, includes a discriminator unit and a timing recovery unit. The output of the discriminator unit is provided as an input to the timing recovery unit, which timing recovery unit is configured to align a free-running clock of the receiver with a received signal to extract received data therefrom.
Claims19
A receiver, comprising:
- a discriminator unit configured to receive an over-sampled data signal as an input;
- and
- a timing recovery unit configured to align a clock signal outputted by a free-running clock with a received data signal present in the over-sampled data signal to extract data therefrom, wherein an output signal of the discriminator unit is provided as an input to the timing recovery unit;
- wherein the timing recovery unit further comprises:
- an edge detector coupled to receive the output signal of the discriminator unit and adapted to detect a rising edge of the output signal;
- a comparator coupled to receive an output of the edge detector and a recovered clock signal extracted from the over-sampled data signal and adapted to compare the received clock signal and received data signal to determine whether the rising edge of the recovered clock signal aliens with a midpoint of the received data signal;
- and
- an edge shifter coupled to receive the output of the edge detector and adapted to advance the recovered clock signal in time when the rising edge of the recovered clock signal is proximate a falling edge of the received data signal and to delay the recovered clock signal when the rising edge of the recovered clock signal is proximate a rising edge of the received data signal.
5 more elements
A digital circuit, comprising:
- a receiving unit coupled to receive a data signal and a clock signal;
- an edge detector coupled to receive an output from the receiving unit and configured to detect a rising edge of the clock signal;
- a comparator coupled to the edge detector and configured to compare the clock signal and the data signal to determine whether the rising edge of the clock signal aligns with a midpoint of the data signal;
- and
- an edge shifter coupled to the edge detector and configured to advance the data signal in time when the rising edge of the clock signal is proximate a falling edge of the data signal and to delay the data signal in time when the rising edge of the clock signal is proximate a rising edge of the data signal.
2 more elements
A method, comprising:
- directly downconverting a radio frequency signal to produce in-phase and quadrature components thereof and filtering the in-phase and quadrature components to produce a pair of received signals;
- demodulating the pair of received signals among a discriminator configured to extract an over-sampled data signal from the pair of received signals and a timing recovery unit configured to align a clock signal generated by a free-running clock with a moving edge of the over-sampled data signal to produce a bit-timing clock used to extract a data signal from the over-sampled data signal;
- wherein the discriminator extracts the over-sampled data signal by logically XORing bit-stored versions of the received signal and the delayed replicas of themselves and filtering a resulting signal.
A method, comprising:
- directly downconverting a radio frequency signal to produce in-phase and quadrature components thereof and filtering the in-phase and quadrature components to produce a pair of received signals;
- demodulating the pair of received signals among a discriminator configured to extract an over-sampled data signal from the pair of received signals and a timing recovery unit configured to align a clock signal generated by a free-running clock with a moving edge of the over-sampled data signal to produce a bit-timing clock used to extract a data signal from the over-sampled data signal;
- wherein the timing recovery unit produces the bit-timing clock by adjusting the free-running clock in time using a counter, and the timing recovery unit extracts the data signal by compressing a leading edge of the over-sampled data signal to the bit-timing clock.
Dependencies are inferred from the claim text.