Output symbol rate control in a packet transport rate conversion system
AssigneeThomson Licensing
InventorsKumar Ramaswamy, Paul Gothard Knutson
Life of this patent
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Abstract
A remodulator system includes a source of an input transport packet stream and an input packet buffer coupled to the input transport packet stream source. The input packet buffer generates a status signal indicating whether it is: full, empty, or neither empty nor full. An output packet stream generator is coupled to the input packet stream buffer and responsive to an output clock signal, and generates the output packet stream in synchronism with the output clock signal. A variable output clock signal generator generates the output clock signal responsive to a control signal, and a control signal generator generates the control signal in response to the status signal.
Claims11
In a remodulator system, apparatus for controlling the bit rate of an output packet stream, comprising:
- a source of an input transport packet stream;
- an input packet buffer, coupled to the input transport packet stream source, for generating a status signal indicating whether the input packet buffer is:
- full, empty, or neither empty nor full;
- a control signal generator, responsive to the said status signal, and generating a control signal;
- a variable output clock signal generator, responsive to said control signal;
- and
- an output packet stream generator coupled to said input packet buffer, and responsive to a variable output clock signal, for generating said output packet stream in synchronism with said variable output clock signal wherein the variable clock signal generator is responsive to the control signal for varying the frequency of the output clock signal;
- and the control signal generator comprises circuitry to generate the control signal to condition the variable output clock signal generator to increase its frequency if the status signal indicates that the input packet buffer is full, and decrease its frequency if the status signal indicates that the input packet buffer is empty.
In a remodulator system, a method for controlling the bit rate of an output packet stream, comprising the steps of:
- providing a source of an input transport packet stream;
- storing input packets from said source in an input packet buffer;
- generating a status signal indicating whether the input packet buffer is;
- full, empty or neither empty nor full;
- generating a control signal in response to said status signal;
- generating a variable output clock signal in response to said control signal;
- and
- generating the output packet stream response to and in synchronism with said variable output clock signal wherein the frequency of the output clock signal varies in response to the control signal;
- and the variable output clock signal increases in frequency if the staus signal indicates that the input packet buffer is full, and decreases in frequency if the status signal indicates that the input packet buffer is empty.
Dependencies are inferred from the claim text.