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US 6,888,777 B2Granted
Address decode
AssigneeIntel Corporation
InventorsJames M. Dodd, Robert Milstrey
Life of this patent
Estimating the term…
Abstract
Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor or other external components provide a memory controller with decoded memory addresses. The memory controller then may access the memory with the processor decoded address without decoding the address itself. In other embodiments, a processor or other external components provide a memory controller with partially decoded memory addresses. The memory controller then generates a decoded address from the partially decoded address and may access the memory with the generated decoded address.
Claims39
A method comprising:
- decoding a first address of a transaction to a memory to generate a second address;
- and
- issuing the transaction to provide a memory controller with the second address, and to request the memory controller to process the transaction based on the second address,
- wherein decoding comprises generating the second address such that the second address comprises a partially decoded address.
1 more element
A method comprising:
- decoding a first address of a transaction to a memory to generate a second address;
- and
- issuing the transaction to provide a memory controller with the second address, and to request the memory controller to process the transaction based on the second address,
- wherein decoding comprises generating the second address such that the second address comprises an intermediate form that the memory controller decodes quicker than a non-decoded address.
1 more element
A method comprising:
- decoding a first address of a transaction to a memory to generate a second address;
- and
- issuing the transaction to provide a memory controller with the second address, and to request the memory controller to process the transaction based on the second address,
- wherein decoding comprises generating the second address such that the second address comprises two or more memory selects, and a format indicator that indicates a format of the second address.
1 more element
A method comprising:
- decoding a first address of a transaction to a memory to generate a second address;
- issuing the transaction to provide a memory controller with the second address, and to request the memory controller to process the transaction based on the second address;
- and
- providing the memory controller with a format indicator that indicates a format of the second address.
1 more element
A method comprising:
- receiving an address of a memory transaction from an external component;
- and
- addressing a memory using the received address in response to determining that the address comprises a decoded address.
A method comprising:
- receiving an address comprising a plurality of memory selects from a external component;
- addressing a memory using the plurality of memory selects;
- and
- forgoing decoding of the address in response to determining that the address is completely decoded.
1 more element
A method comprising:
- receiving an address comprising a plurality of memory selects from a external component;
- addressing a memory using the plurality of memory selects;
- and
- in response to determining that the address is partially decoded:
- decoding the address to generate one or more additional memory selects;
- and
- addressing the memory using also the one or more additional memory selects.
4 more elements
A processor comprising:
- an address decoder to generate one or more memory selects based upon an address of a memory transaction;
- and
- a bus interface to issue the memory transaction and to provide an address comprising the one or more memory selects,
- wherein the bus interface is to further provide a format indicator that indicates that the address comprises the one or more memory selects.
1 more element
A memory controller comprising:
- a request interface to receive a first address of a memory transaction;
- a memory interface to address a memory;
- and
- control logic to cause the memory interface to address the memory using the first address in response to determining that the first address comprises a decoded address.
1 more element
A system comprising:
- volatile memory comprising storage locations arranged in a hierarchal manner;
- a processor to generate from a first address of a memory transaction a second address comprising a plurality of memory selects and to issue the memory transaction on a processor bus to request processing of the memory transaction and to provide the second address;
- and
- a memory controller coupled to the processor via the processor bus and to the volatile memory via a memory bus, the memory controller to receive the memory transaction and the second address via the processor bus and to apply the plurality of memory selects of the second address to the memory bus.
1 more element
A machine-readable medium comprising a plurality of instructions that in response to being executed result in a processor:
- decoding a first address of a transaction to a memory to generate a second address;
- issuing the transaction to provide a memory controller with the second address, and to request the memory controller to process the transaction based on the second address;
- generating a format indicator that indicates the second address is decoded;
- and
- providing the memory controller with the format indicator.
2 more elements
A machine-readable medium comprising a plurality of instructions that in response to being executed result in a processor:
- decoding a first address of a transaction to a memory to generate a second address;
- issuing the transaction to provide a memory controller with the second address, and to request the memory controller to process the transaction based on the second address;
- generating a format indicator that indicates that the second address is partially decoded;
- and
- providing the memory controller with the format indicator.
2 more elements
A processor comprising:
- circuitry to execute instructions,
- an address decoder to generate one or more memory selects based upon an address of a memory transaction;
- and
- a bus interface to issue the memory transaction and to provide an address comprising the one or more memory selects.
1 more element
A processor comprising
- circuitry to execute instructions,
- an address decoder to decode a first address of a memory transaction to a second address for the memory transaction, and
- a bus interface to issue the memory transaction and to provide the second address for the memory transaction.
Dependencies are inferred from the claim text.