US 6,888,775 B2Granted

Semiconductor memory device for improvement of defective data line relief rate

AssigneeRenesas Technology Corp.

InventorJun Ohtani

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Abstract

A semiconductor memory device according to the present invention includes: a data line switching circuit including a plurality of switches which selectively connect one of a plurality of normal data lines and spare data lines included in a memory cell array to one of a plurality of global data lines for transmitting input/output data to the memory cell array; and a switching control circuit including a shift decoder having decode circuits for decoding a defective address stored in a program circuit as many as the switches.

Claims7

Dependent claims

A semiconductor memory device comprising:

a memory cell array having a plurality of memory cells arranged therein,
said memory cell array including (L+M) local data lines numbered first to (L+M)th in order in advance, where L is an integer not less than 2 and M is a natural number less than the L,
said (L+M) local data lines including:
L normal data lines transmitting input/output data in parallel;
and
M spare data lines, each provided to relieve a defect for each normal data line among said L normal data lines,
said semiconductor memory device further comprising:
L global data lines for transmitting said input/output data to said memory cell array;
a data line switching circuit provided between said (L+M) local data lines and said L global data lines;
and
a switching control circuit for controlling said data line switching circuit,
said data line switching circuit including L switch circuits provided in correspondence with said L global data lines, respectively,
among said L switch circuits, the Jth switch circuit selectively connecting the corresponding Jth global data line to one of the Jth to (J+K)th local data lines among said (L+M) local data lines in accordance with an indicated shift count K, where J is a natural number not more than the L, and K is an integer not less than 0 and not more than M,
said switching control circuit including:
M program circuits, each capable of storing a defective address for specifying the normal data line corresponding to said defect among said L normal data lines;
M first decoders provided in correspondence with said M program circuits, respectively;
and
a second decoder indicating said shift count K to each of said L switch circuits in accordance with M outputs of said M program circuits,
each of said M first decoders outputting, in parallel, L determination results as to whether a shift according to each of said L switch circuits can be made when said normal data line corresponding to said defective address stored in the corresponding program circuit is relieved, and
said second decoder calculating L of said shift count K, respectively corresponding to said L switch circuits, in accordance with M sets of said L determination results outputted from said M first decoders, respectively.

17 more elements

Dependencies are inferred from the claim text.

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Abstract

A semiconductor memory device comprising:

a memory cell array having a plurality of memory cells arranged therein,
said memory cell array including (L+M) local data lines numbered first to (L+M)th in order in advance, where L is an integer not less than 2 and M is a natural number less than the L,
said (L+M) local data lines including:
L normal data lines transmitting input/output data in parallel;
and
M spare data lines, each provided to relieve a defect for each normal data line among said L normal data lines,
said semiconductor memory device further comprising:
L global data lines for transmitting said input/output data to said memory cell array;
a data line switching circuit provided between said (L+M) local data lines and said L global data lines;
and
a switching control circuit for controlling said data line switching circuit,
said data line switching circuit including L switch circuits provided in correspondence with said L global data lines, respectively,
among said L switch circuits, the Jth switch circuit selectively connecting the corresponding Jth global data line to one of the Jth to (J+K)th local data lines among said (L+M) local data lines in accordance with an indicated shift count K, where J is a natural number not more than the L, and K is an integer not less than 0 and not more than M,
said switching control circuit including:
M program circuits, each capable of storing a defective address for specifying the normal data line corresponding to said defect among said L normal data lines;
M first decoders provided in correspondence with said M program circuits, respectively;
and
a second decoder indicating said shift count K to each of said L switch circuits in accordance with M outputs of said M program circuits,
each of said M first decoders outputting, in parallel, L determination results as to whether a shift according to each of said L switch circuits can be made when said normal data line corresponding to said defective address stored in the corresponding program circuit is relieved, and
said second decoder calculating L of said shift count K, respectively corresponding to said L switch circuits, in accordance with M sets of said L determination results outputted from said M first decoders, respectively.

17 more elements