Non-volatile memory device achieving fast data reading by reducing data line charging period

A non-volatile memory device, comprising:

• a plurality of memory cells, through each of said plurality of memory cells a pass current corresponding to a stored data flowing in a data reading operation;
• a plurality of bit lines, at least one of said plurality of bit lines being connected to a first voltage via a selected memory cell corresponding to a selected address among said plurality of memory cells in said data reading operation;
• a data line commonly provided to said plurality of bit lines for electrically coupling to said at least one of said plurality of bit lines in said data reading operation;
• a reference current supplying unit generating a reference current used for a comparison with said selected memory cell;
• a differential amplifier connected to a second voltage in said data reading operation for supplying a pass current to said data line, and for reading said stored data of said selected memory cell corresponding to a current difference between said pass current and said reference current generated by said reference current supplying unit;
• a capacitive element provided corresponding to said data line, and formed with a metal insulator semiconductor field effect transistor having its gate electrically coupled to said data line;
• and
• a signal line electrically coupled to source and drain of said capacitive element;
• wherein
• said capacitive element raises a level of said data line for a prescribed period.