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US 6,888,771 B2Granted
Skewed sense AMP for variable resistance memory sensing
AssigneeMicron Technology, Inc.
InventorsGlen Hush, R. Jacob Baker, John Moore
Life of this patent
Estimating the term…
Abstract
A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance state. The built-in offset can be achieved by varying size, threshold voltage, associated capacity or associated resistance of the transistors within the sense amplifier.
Claims39
A memory circuit comprising:
- a variable resistance memory cell;
- a circuit for selectively applying a voltage differential across said memory cell, said circuit comprising:
- a precharge circuit for precharging a pair of conductive lines to said differential voltage and a selection circuit for selectively connecting said variable resistance memory cell across said precharged pair of conductive lines;
- and
- a sense amplifier selectively coupled across said memory cell for determining a logic state of said cell based on a voltage state existing across said cell at a predetermined period of time after said differential voltage is applied.
2 more elements
A memory circuit comprising:
- a variable resistance memory cell;
- a circuit for selectively applying a voltage differential across said memory cell;
- and
- a sense amplifier selectively coupled across said memory cell for determining a logic state of said cell based on a voltage state existing across said cell at a predetermined period of time after said differential voltage is applied;
- wherein said sense amplifier has an unbalanced voltage sensing characteristic.
2 more elements
A memory circuit comprising:
- a variable resistance memory cell;
- a circuit for selectively applying a voltage differential across said memory cell;
- and
- a sense amplifier selectively coupled across said memory cell for determining a logic state of said cell based on a voltage state existing across said cell at a predetermined period of time after said differential voltage is applied;
- wherein said voltage differential is produced by different positive voltages respectively applied to opposite sides of said memory cell.
2 more elements
A memory circuit comprising:
- a memory cell having a variable resistance;
- a sense amplifier for measuring resistance of said memory cell and connected to said memory cell via first and second column lines, said sense amplifier comprising:
- a pair of cross-coupled transistors;
- and
- a transistor connected to said pair of cross-coupled transistors and coupled to a first sense line
- wherein said cross-coupled transistors differ from each other in operational characteristics so that sensing offset voltage exists between them.
3 more elements
A memory circuit comprising:
- a memory cell having a variable resistance;
- and
- a sense amplifier for measuring the resistance within said memory cell and connected to said memory cell via first and second column lines, said sense amplifier comprising:
- a first pair of cross-coupled transistors of a first conductivity;
- a second pair of cross-coupled transistors of a second conductivity connected adjacent to said first pair of cross-coupled transistors;
- a transistor of said first conductivity connected to said first pair and coupled to a first sense line;
- and
- a transistor of said second conductivity connected to said second pair and coupled to a second sense line;
- wherein said pair of first cross-coupled transistors differ from each other in operational characteristics so that a sensing offset voltage exists between them.
6 more elements
A method of sensing a variable resistance memory cell, comprising:
- setting a pair of column lines to a predetermined differential voltage;
- selectively connecting said memory cell across said column lines;
- operating a sense amplifier coupled at respective inputs to said column lines a predetermined period of time after said selected memory cell receives said differential voltage from said column lines, to determine a resistance state of said memory cell.
A processor circuit comprising:
- a processor;
- and
- a memory device for exchanging data with said processor, said memory device comprising:
- a variable resistance memory cell;
- a circuit for selectively applying a voltage differential across said memory cell, said circuit comprising a precharge circuit for precharging a pair of conductive lines to said differential voltage and a selection circuit for selectively connecting said variable resistance memory cell across said precharged pair of conductive lines;
- and
- a sense amplifier selectively coupled across said memory cell for determining a logic state of said cell based on a voltage state existing across said cell at a predetermined period of time after said differential voltage is applied.
4 more elements
A processor circuit comprising:
- a processor;
- and
- a memory device for exchanging data with said processor, said memory device comprising:
- a variable resistance memory cell;
- a circuit for selectively applying a voltage differential across said memory cell;
- and
- a sense amplifier selectively coupled across said memory cell for determining a logic state of said cell based on a voltage state existing across said cell at a predetermined period of time after said differential voltage is applied;
- wherein said sense amplifier has an unbalanced voltage sensing characteristic which provides said input sensing offset voltage.
5 more elements
A processor circuit comprising:
- a processor;
- and
- a memory device for exchanging data with said processor, said memory device comprising:
- a variable resistance memory cell;
- a circuit for selectively applying a voltage differential across said memory cell;
- and
- a sense amplifier selectively coupled across said memory cell for determining a logic state of said cell based on a voltage state existing across said cell at a predetermined period of time after said differential voltage is applied;
- wherein said voltage differential is produced by different positive voltages respectively applied to opposite sides of said memory cell.
5 more elements
A memory sense circuit, comprising:
- a first and second column line;
- a variable memory element which can be selectively connected across said column lines;
- a precharge circuit for precharging said column lines to a predetermined differential voltage;
- and
- a sense circuit for sensing a voltage across said column lines at a predetermined period of time after said resistance is selectively connected across said column lines.
2 more elements
Dependencies are inferred from the claim text.