Dual power sensing scheme for a memory device

A method for recycling charge comprising:

• powering at least a portion of sensing operations of a first array of bit line sense operations with first and second power lines at an upper reference voltage level and a first intermediate voltage level, respectively;
• powering at least a portion of sensing operations of a second array of bit line sense operations with first and second power lines at a second intermediate voltage level and a lower reference voltage level, respectively;
• and
• during or prior to the sensing operations, transferring charge from the second power line of the first array to the first power line of the second array.

A method for recycling charge from one or more power lines of a first array of bit line sense amplifiers to one or more power lines of a second array of bit line sense amplifiers, comprising:

• momentarily closing a first one or more switches to precharge first and second power lines of the first array to a first voltage level between a first intermediate voltage level and an upper reference voltage level and to precharge first and second power lines of the second array to a second voltage level between a lower reference voltage level and a second intermediate voltage level;
• momentarily closing a second one or more switches to transfer charge from the second power line of the first array to the first power line of the second array;
• and
• momentarily closing a third one or more switches to couple the first power line of the second array to a power supply node at the second intermediate voltage level.

A circuit configuration for use in recycling bit line charges comprising:

• a first set of switches to selectively couple a first power line of a first array of bit line sense amplifiers to a power supply node at an upper reference voltage level and to selectively couple a second power line of a second array of bit line sense amplifiers to a power supply node at a lower reference voltage level;
• a second set of switches to selectively couple a second power line of the first array to a power supply node at a first intermediate voltage level and to selectively couple a first power line of the second array to a power supply node at a second intermediate voltage level higher than the first intermediate voltage level;
• a third set of switches to selectively precharge the first and second power lines of the first array to a first precharge voltage level and to selectively precharge the first and second power lines of the second array to a second precharge voltage level;
• and
• a fourth set of one or more switches to selectively couple the second power line of the first array to the first power line of the second array.

A memory device comprising:

• at least first and second arrays of bit line sense amplifiers to sense bit lines of memory cells of the memory device;
• a voltage regulator with output nodes for at least an upper voltage reference, first and second intermediate voltages, and a lower voltage reference;
• and
• sensing control circuitry configured to precharge first and second power lines of the first array to a first precharge level, precharge first and second power lines of the second array to a second precharge level, transfer charge from the second power line of the first array to the first line of the second array, couple the second power line of the first array to the first intermediate voltage output node, and couple the first power line of the second array to the second intermediate voltage output node.