Semiconductor memory device provided with test memory cell unit

A semiconductor memory device comprising:

• a memory cell block which includes a memory cell unit having a plurality of memory cells each containing a ferroelectric capacitor, and a test memory cell unit having a plurality of test memory cells,
• wherein a layout pattern of said test memory cells is identical to a layout pattern of said memory cells, and said test memory cell unit is provided adjacently to said memory cell unit,
• said memory cell block comprises a redundancy memory cell unit, and
• said redundancy memory cell unit is said test memory cell unit, and said test memory cells are redundancy memory cells.

A semiconductor memory device which is provided with a memory cell block comprising a memory cell unit having a plurality of memory cells each containing a ferroelectric capacitor, and a test memory cell unit having a plurality of test memory cells, a layout pattern of said test memory cells being identical to a layout pattern of said memory cells, and said test memory cell unit being provided adjacently to said memory cell unit,

• wherein said semiconductor memory device is subjected to a screening test such that:
• a first screening test is conducted on both said memory cell unit and said test memory cell unit, and then
• a second screening test is conducted only on said test memory cell unit,
• a total number of test cycles of the first and second screening tests corresponding to an assurance number of cycles.

In a semiconductor memory device provided with a memory cell block comprising a memory cell unit having a plurality of memory cells each containing a ferroelectric capacitor, and a test memory cell unit having a plurality of test memory cells, a layout pattern of the test memory cells being identical to a layout pattern of the memory cells, and the test memory cell unit being provided adjacently to said memory cell unit,

• a screening test comprising:
• a first screening test conducted on both the memory cell unit and the test memory cell unit;
• and
• a second screening test conducted only on the test memory cell unit,
• a total number of test cycles of the first and second screening tests corresponding to an assurance number of cycles.