Integrated circuit and method for testing same using single pin to control test mode and normal mode operation

An integrated circuit, comprising:

• an external node;
• operational circuitry;
• and
• test circuitry coupled to the external node and the operational circuitry, wherein the test circuitry is configured to operate in at least one test mode in response to test data received at the external node from an external source, and the test circuitry is configured to assert to the operational circuitry a control signal in response to an external control signal received at the external node, wherein the test circuitry is configured to extract the test data from an amplitude-modulated input signal asserted to the external node from the external source, and to generate the control signal in response to the input signal, wherein the input signal has at least three levels, including a low level below a first threshold, a high level above a second threshold, and an intermediate level between the first threshold and the second threshold, and wherein the test circuitry includes:
• first comparator circuitry, coupled to receive the input signal and configured to operate in a first mode in which said first comparator circuitry generates a first signal indicative of whether the input signal has a level less than the first threshold;
• second comparator circuitry, coupled to receive the input signal and configured to operate in a first mode in which said second comparator circuitry generates a second signal indicative of whether the input signal has a level greater than the second threshold;
• and
• logic circuitry coupled and configured to generate a second control signal in response to the input signal, and to assert the second control signal to the first comparator circuitry and the second comparator circuitry, wherein the second control signal is indicative of whether the input signal has a level that has remained below the first threshold for at least a predetermined minimum time, and wherein the second control signal disables each of the first comparator circuitry and the second comparator circuitry from operating in the first mode when the second control signal indicates that the level of input signal has remained below the first threshold for at least the predetermined minimum time.

An integrated circuit, comprising:

• an external node;
• operational circuitry;
• and
• test circuitry coupled to the external node and the operational circuitry, wherein the test circuitry is configured to operate in at least one test mode in response to test data received at the external node from an external source, and the test circuitry is configured to assert to the operational circuitry a control signal in response to an external control signal received at the external node, wherein the test circuitry is configured to extract the test data from an amplitude-modulated input signal asserted to the external node from the external source, and to generate the control signal in response to the input signal, wherein the input signal has at least four levels, including a low level below a first threshold, a high level above a second threshold, an intermediate level between the first threshold and the second threshold, and a latch level above a third threshold, where the third threshold is greater than the second threshold, and wherein the test circuitry includes:
• first comparator circuitry, coupled to receive the input signal and configured to operate in a first mode in which said first comparator circuitry generates a first signal indicative of whether the input signal has a level less than the first threshold;
• second comparator circuitry, coupled to receive the input signal and configured to operate in a first mode in which said second comparator circuitry generate a second signal indicative of whether the input signal has a level greater than the second threshold;
• and
• third comparator circuitry, coupled and configured to generate a latch signal indicative of whether the input signal has a level greater than the third threshold.

An integrated circuit, comprising:

• an external node;
• operational circuitry;
• and
• test circuitry coupled to the external node and the operational circuitry, wherein the test circuitry is configured to operate in at least one test mode in response to test data received at the external node from an external source, and the test circuitry is configured to assert to the operational circuitry a control signal in response to an external control signal received at the external node, wherein the test circuitry is configured to extract the test data from an amplitude-modulated input signal asserted to the external node from the external source, and to generate the control signal in response to the input signal, wherein the test circuitry includes:
• comparator circuitry coupled and configured to receive the input signal, to extract the test data from the input signal, and to extract a latch signal from the input signal wherein the latch signal is indicative of whether the input signal has a level exceeding a latch threshold;
• at least one register coupled to the comparator circuitry for receiving the latch signal and at least some of the test data;
• and
• a nonvolatile memory comprising at least one programmable cell having a first input coupled to receive a sequence of bits of the test data, and a second input coupled to receive a programming voltage, wherein the cell is operable in a mode in which the cell stores one of the bits of the test data being asserted at the first input while the programming voltage exceeds a programming level.

An integrated circuit, comprising:

• an external node;
• operational circuitry;
• and
• test circuitry coupled to the external node and the operational circuitry, wherein the test circuitry is configured to operate in at least one test mode in response to test data received at the external node from an external source, and the test circuitry is configured to assert to the operational circuitry a control signal in response to an external control signal received at the external node, wherein the test circuitry is configured to extract the test data from an amplitude-modulated input signal asserted to the external node from the external source, and to generate the control signal in response to the input signal, and wherein the test circuitry includes:
• a nonvolatile memory comprising at least one programmable cell having a first input coupled to receive a sequence of bits of the test data, and a second input coupled to receive a programming voltage, wherein the cell is operable in a mode in which the cell stores one of the bits of the test data being asserted at the first input while the programming voltage exceeds a programming level.

An integrated circuit, comprising:

• an external node;
• operational circuitry;
• and
• test circuitry coupled to the external node and the operational circuitry, wherein the test circuitry is configured to operate in at least one test mode in response to test data received at the external node from an external source, and the test circuitry is configured to assert to the operational circuitry a control signal in response to an external control signal received at the external node, wherein the test circuitry is configured to extract the test data from an input signal asserted to the external node from the external source, and wherein the test circuitry includes:
• a timeout circuit coupled and configured to terminate operation of the test circuitry in each said test mode unless bits of the lest data occur at the external node with frequency not less than a predetermined minimum frequency.

An integrated circuit, comprising:

• an external node;
• operational circuitry;
• and
• test circuitry coupled to the external node and the operational circuitry, wherein the test circuitry is configured to operate in at least one test mode in response to test data received at the external node from an external source, and the test circuitry is configured to assert to the operational circuitry a control signal in response to an external control signal received at the external node, wherein the test circuitry includes:
• logic circuitry coupled and configured to extract the test data from an input signal asserted to the external node from the external source;
• lock circuitry coupled to receive the test data, and operable to analyze the test data to determine whether said test data is indicative of a digital key, and to generate a second control signal in response to determining that said test data is indicative of the digital key;
• and
• additional circuitry, coupled to the logic circuitry and configured to perform at least one test mode operation when the test circuitry is in each said test mode, wherein the lock circuitry asserts the second control signal to the additional circuitry to initiate each said test mode of the test circuitry.

Test circuitry suitable for use in a circuit comprising an access node, and operational circuitry configured to operate in response to at least one control signal asserted to the access node, said test circuitry comprising:

• logic circuitry configured to be coupled to the access node and to the operational circuitry;
• and
• additional circuitry coupled to the logic circuitry and configured to operate in at least one test mode in response to test data received at the access node,
• wherein the logic circuitry is configured to extract the test data from an amplitude-modulated input sigal asserted to the access node when the logic circuitry is coupled to the access node, and to generate the control signal in response to the input signal such that the control signal has a state determined by the input signal but not by the test data, and assert said control signal to the operational circuitry when the logic circuitry is coupled to the access node and to the operational circuitry.

Test circuitry suitable for use in a circuit comprising an access node, and operational circuitry configured to operate in response to at least one control signal asserted to the access node, said test circuitry comprising:

• logic circuitry configured to be coupled to the access node and to the operational circuitry;
• and
• additional circuitry coupled to the logic circuitry and configured to operate in at least one test mode in response to lost data received at the access node,
• wherein the logic circuitry is configured to extract the test data from an amplitude-modulated input signal asserted to the access node when the logic circuitry is coupled to the access node, and to generate the control signal in response to the input signal and assert said control sigal to the operational circuitry when the logic circuitry is coupled to the access node and to the operational circuitry, wherein the input signal has at least four levels, including a low level below a first threshold, a high level above a second threshold, an intermediate level between the first threshold and the second threshold, and a latch level above a third threshold, where the third threshold is greater than the second threshold, and wherein the logic circuitry includes:
• first comparator circuitry, configured to be coupled to receive the input signal and to operate in a first mode in which said first comparator circuitry generates a first signal indicative of whether the input signal has a level less than the first threshold;
• second comparator circuitry, configured to be coupled to receive the input signal and to operate in a first mode in which said second comparator circuitry generates a second signal indicative of whether the input signal has a level greater than the second threshold;
• and
• third comparator circuitry, coupled and configured to generate a latch signal indicative of whether the input signal has a level greater than the third threshold.

Test circuitry suitable for use in a circuit comprising an access node, and operational circuitry configured to operate in response to at least one control signal asserted to the access node, said test circuitry comprising:

• logic circuitry configured to be coupled to the access node and to the operational circuitry;
• and
• additional circuitry coupled to the logic circuitry and configured to operate in at least one test mode in response to test data received at the access node, wherein the logic circuitry is configured to extract the test data from an amplitude-modulated input signal asserted to the access node when the logic circuitry is coupled to the access node, and to generate the control signal in response to the input signal and assert said control signal to the operational circuitry when the logic circuitry is coupled to the access node and to the operational circuitry, and wherein the additional circuitry includes:
• a nonvolatile memory comprising at least one programmable cell having a first input coupled to receive a sequence of bits of the test data, and a second input coupled to receive a programming voltage, wherein the cell is operable in a mode in which the cell stores one of the bits of the test data being asserted at the first input while the programming voltage exceeds a programming level.

Test circuitry suitable for use in a circuit comprising an access node, and operational circuitry configured to operate in response to at least one control signal asserted to the access node, said test circuitry comprising:

• logic circuitry configured to be coupled to the access node and to the operational circuitry;
• and
• additional circuitry coupled to the logic circuitry and configured to operate in at least one test mode in response to test data received at the access node, wherein the logic circuitry is configured to extract the test data from an amplitude-modulated input signal asserted to the access node when the logic circuitry is coupled to the access node, and to generate the control signal in response to the input signal and assert said control signal to the operational circuitry when the logic circuitry is coupled to the access node and to the operational circuitry, wherein the logic circuitry includes comparator circuitry coupled and configured to receive the input signal, to extract the test data from the input signal, and to extract a latch signal from the input signal, wherein the latch signal is indicative of whether the input signal has a level exceeding a latch threshold, and
• wherein the additional circuitry includes:
• at least one register coupled to the comparator circuitry for receiving the latch signal and at least some of the test data;
• a nonvolatile memory comprising at least one programmable cell having a first input coupled to receive a sequence of bits of the test data, and a second input coupled to receive a programming voltage, wherein the call is operable in a mode in which the cell stores one of the bits of the test data being asserted at the first input while the programming voltage exceeds a programming level;
• and
• a switch, coupled between the access node and the second input of the cell, wherein the switch has a closed state in which it passes the input signal to the second input of the cell, and wherein the input signal is said programming voltage.

A method for controlling operational circuitry within an integrated circuit, and performing at least one of testing, configuration, and reconfiguration of the operational circuitry, wherein the integrated circuit has an external node and the operational circuitry is configured to operate in response to at least one control signal, said method including the steps of:

• operating test circuitry of the integrated circuit in at least one test mode in response to test data received at the external node from an external source, wherein the test circuitry includes a nonvolatile memory comprising at least one programmable cell;
• asserting said at least one control signal from the test circuitry to the operational circuitry in response to an external control signal received at the external node;
• and
• extracting the test data from an amplitude-modulated input signal asserted to the external node from the external source, and generating said at least one control signal in response to the input signal;
• during each said test mode, generating a latch signal in response to determining that the input signal has a level above a latch threshold;
• and
• capturing a bit of the test data at said cell in response to the latch signal.

A method for controlling operational circuitry within an integrated circuit, and performing at least one of testing, configuration, and reconfiguration of the operational circuitry, wherein the integrated circuit has an external node and the operational circuitry is configured to operate in response to at least one control signal, said method including the steps of:

• operating test circuitry of the integrated circuit in at least one test mode in response to test data received at the external node from an external source;
• asserting said at least one control signal from the test circuitry to the operational circuitry in response to an external control signal received at the external node;
• extracting the test data from an amplitude-modulated input signal assented to the external node from the external source;
• and
• when operating the test circuitry in each said test mode, terminating test mode operation of the test circuitry unless bits of the test data occur at the external node with frequency not less than a predetermined minimum frequency.

A method for controlling operational circuitry within an integrated circuit, and performing at least one of testing, configuration, and reconfiguration of the operational circuitry, wherein the integrated circuit has an external node and the operational circuitry is configured to operate in response to at least one control signal, said method including the steps of:

• operating test circuitry of the integrated circuit in at least one test mode in response to test data received at the external node from an external source;
• asserting said at least one control signal from the test circuitry to the operational circuitry in response to an external control signal received at the external node;
• extracting the test data from an input signal asserted to the external node from the external source;
• and
• analyzing the test data to determine whether said test data is indicative of a key, and commencing operation of the test circuitry in each said test mode only in response to determining that said test data is indicative of the key.