Memory device having simultaneous read/write and refresh operations with coincident phases
AssigneeBroadcom Corporation
InventorsCyrus Afghahi, Sami Issa
Life of this patent
Estimating the term…
Abstract
A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.
Claims21
A memory circuit comprising:
- a plurality of memory cells, organized into columns and rows, that are accessed during memory access cycles, which include refresh cycles and read/write cycles, wherein the memory cells are substantially continuously refreshed using the refresh cycles;
- a plurality of sense amplifiers, wherein each said sense amplifier is coupled to a corresponding one of the columns of the memory cells, and is used to read data stored in the memory cells of the corresponding column during read phases of the refresh cycles and the read/write cycles;
- and
- a plurality of write amplifiers, wherein each said write amplifier is coupled to a corresponding one of the columns of the memory cells of the corresponding column, and is used to write data to the memory cells during write phases of the memory access cycles,
- wherein the read phases of the refresh cycles substantially coincide with the write phases of the read/write cycles, and the write phases of the refresh cycles substantially coincide with the read phases of the read/write cycles.
A method of refreshing memory cells organized into columns and rows, the memory cells being accessed during memory access cycles, which include refresh cycles and read/write cycles, the method comprising:
- reading data stored in the memory cells during read phases of the memory access cycles, wherein same sense amplifiers are used to read the memory cells during both the refresh cycles and the read/write cycles;
- and
- writing data to the memory cells during write phases of the memory access cycles,
- wherein the memory cells are substantially continuously refreshed, and
- wherein the read phases of the refresh cycles substantially coincide with the write phases of the read/write cycles, and the write phases of the refresh cycles substantially coincide with the read phases of the read/write cycles.
A system-on-chip (SOC) device comprising:
- data processing circuitry for processing input data to generate output data;
- an I/O port for receiving the input data and for outputting the output data;
- and
- a memory block comprising:
- a plurality of memory cells, organized into columns and rows, that are accessed during memory access cycles, which include refresh cycles and read/write cycles, wherein the memory cells are substantially continuously refreshed using the refresh cycles;
- a plurality of sense amplifiers, wherein each said sense amplifier is coupled to a corresponding one of the columns of the memory cells, and is used to read data stored in the memory cells of the corresponding column during read phases of the refresh cycles and the read/write cycles, wherein the data processing circuitry processes the input data based on the data stored in the memory cells to generate the output data;
- and
- a plurality of write amplifiers, wherein each said write amplifier is coupled to a corresponding one of the columns of the memory cells of the corresponding column, and is used to write data to the memory cells during write phases of the memory access cycles,
- wherein the read phases of the refresh cycles substantially coincide with the write phases of the read/write cycles, and the write phases of the refresh cycles substantially coincide with the read phases of the read/write cycles.
Dependencies are inferred from the claim text.