System and method for multiplexing data and data masking information on a data bus of a memory device
AssigneeMicron Technology, Inc.
InventorPaul A. LaBerge
Life of this patent
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Abstract
A method and system masking data being written to a memory device having a data bus. One method includes applying masking data on the data bus, storing the masking data in the memory device, applying write data on the data bus, storing the write data in the memory device, and applying the stored masking data to mask the stored write data.
Claims31
A method of masking data being written to a memory device during a write partial mode, the memory device including data, control, and address busses, the method comprising:
- receiving data words and data masking words on the data bus,
- storing at least one of the data masking words and at least one of the data words,
- applying at least one of the stored data masking words to mask at least one of the stored data words thereby producing at least one masked data word;
- applying at least one masked data word to the memory-cell array.
A read/write circuit adapted to receive data words and data masking words on a data bus, the read/write circuit operable during a write-partial mode to store at least one data masking word and at least one data word applied on the data bus, and operable to apply the at least one data masking word to mask the at least one data word and to thereafter apply the at least one data word to the memory-cell array.
A read/write circuit adapted to receive data words and data masking words applied on a data bus, and operable during a write mode to store data words applied on the data bus and apply the data words to the memory-cell array, and operable during a write-partial mode to store at least one data masking word and at least one data word applied on the data bus, and operable to apply masking data contained in at least one of the data masking words to selectively mask and not mask data contained in at least one of the data words, and to thereafter apply the masked and not masked data to the memory-cell array.
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder and control circuit;
- a read/write circuit coupled to the data bus and the memory-cell array, the read/write circuit operable during a write-partial mode to receive at least one data masking word and at least one data word applied on the data bus and store the received words, and operable to apply the at least one data masking word to mask at least one of the data words and to thereafter apply at least one of the masked data words to the memory-cell array.
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder and control circuit;
- a read/write circuit coupled to the data bus and the memory-cell array, the read/write circuit operable during a write-partial mode to receive at least one data masking word and at least one data word on the data bus and store the received words, and operable to apply the at least one data masking word to mask at least of the data words and to thereafter apply at least one of the masked data word to the memory-cell array.
A method of masking data being written to a memory device, the memory device including a data bus, the method comprising:
- applying masking data on the data bus;
- storing the masking data in the memory device;
- applying write data on the data bus;
- storing the write data in the memory device;
- and
- applying the stored masking data to mask the stored write data.
Dependencies are inferred from the claim text.