Method for erasing a memory cell
AssigneeSaifun Semiconductors Ltd.
InventorsEli Lusky, Boaz Eitan
Life of this patent
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Abstract
A method for erasing a bit of a memory cell in a non-volatile memory cell array, the method comprising applying an erase pulse to at least one bit of at least one memory cell of the array, waiting a delay period wherein a threshold voltage of the at least one memory cell drifts to a different magnitude than at the start of the delay period, and after the delay period, erase verifying the at least one bit to determine if the at least one bit is less than a reference voltage level.
Claims13
A method for erasing a bit of a memory cell in a non-volatile memory cell array, the method comprising:
- applying an erase pulse to at least one bit of at least one memory cell of said array;
- waiting a delay period wherein a threshold voltage of said at least one memory cell drifts to a different magnitude than at the start of the delay period;
- and
- after said delay period, erase verifying said at least one bit to determine if said at least one bit is less than a reference voltage level.
A non-volatile memory cell array comprising:
- a plurality of memory cells;
- a power supply adapted to generate erase pulses to bits of said cells;
- and
- a controller in communication with said power supply, said controller adapted to perform the steps of:
- applying an erase pulse to at least one bit of at least one memory cell of said array;
- waiting a delay period wherein a threshold voltage of said at least one memory cell drifts to a different magnitude than at the start of the delay period;
- and
- after said delay period, erase verifying said at least one bit to determine if said at least one bit is less than a reference voltage level.
Dependencies are inferred from the claim text.