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US 6,888,755 B2Granted
Flash memory cell arrays having dual control gates per memory cell charge storage element
AssigneeSanDisk Corporation
InventorEliyahou Harari
Life of this patent
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AssigneeSanDisk Corporation
InventorEliyahou Harari
Estimating the term…
A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.
In a non-volatile memory including an array of charge storage elements positioned over a substrate surface between source and drain regions, a method of altering or determining charge states of designated ones of the storage elements, comprising:
In a non-volatile memory including an array of charge storage elements positioned across a substrate surface, a method of coupling voltages to designated ones of the storage elements for simultaneously programming or reading their charge storage states representative of data stored thereby, comprising applying different voltages to a plurality of control gates having lengths extending across the array between charge storage elements that are capacitively coupled with a pair of the plurality of control gates on either side thereof, including placing first voltage levels on those of the plurality of control gates adjacent the designated storage elements and second voltage levels on those of the plurality of control gates not adjacent to the designated storage elements, wherein the first and second voltages are significantly different.
Dependencies are inferred from the claim text.