US 6,888,754 B2 · Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities

Abstract

This invention provides a memory array and its peripheral circuit with byte-erase capability. The advantage of this invention is the ability to access bytes for program, erase, and read operations. This invention allows this access with the addition of one word line switch and one source line switch for each byte to be accessed for program, erase, and read operations. Also, this invention utilizes a new bias condition to lessen the voltage stress on the high voltage device. In addition, this invention utilizes separate and dedicated power supplies for the local word line driver circuits and for the local source line driver circuits. This is coupled with the partitioning of the main memory array into sub-arrays of 8 columns. This allows the placing of high voltage only on the selected 8 column (byte) subarray. This also substantially lessens the voltage stress on the memory cells and enhances long-term reliability.

Claims31

Dependent claims

A memory array and its peripheral circuit with byte-erase capability comprising:

a first local word line driver, which connects to a first set of control gates of memory cells which store data on a first set of byte;
a second local word line driver, which connects to a second set of control gates of memory cells which store data on a second set of byte;
a first local source line driver, which connects to a first set of source lines of memory cells which store data on said first set of byte;
a second local source line driver, which connects to said source lines of memory cells which store data on said second set of byte;
and
a floating gate memory cell whose drain is connected to a bit line and whose source is connected to said first or second local source line driver, and whose control gate is connected to said first or second local word line driver,
wherein said bit line is shared with other unselected memory cells.

4 more elements

A method for producing a memory array and its peripheral circuit with byte-erase capability comprising the steps of:

including a first local word line driver, which connects to a first set of control gates of memory cells which store data on a first set of byte;
including a second local word line driver, which connects to a second set of control gates of memory cells which store data on a second set of byte;
including a first local source line driver, which connects to a first set of source lines of memory cells which store data on said first set of byte;
including a second local source line driver, which connects to said source lines of memory cells which store data on said second set of byte;
and
including a floating gate memory cell whose drain is connected to a bit line and whose source is connected to said first or second local source line driver, and whose control gate is connected to said first or second local word line driver, and
wherein said bit line is shared with other unselected memory cells.

4 more elements

Dependencies are inferred from the claim text.

Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities

Life of this patent

Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities

Life of this patent

Abstract

Claims31