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US 6,888,747 B2Granted
Methods of reading junction-isolated depletion mode ferroelectric memory devices
AssigneeMicron Technology, Inc.
InventorsCraig T. Salling, Brian W. Huber
Life of this patent
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Abstract
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
Claims19
A method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
- applying a first fraction of a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell;
- applying a ground potential to other word lines coupled to control gates of non-selected memory cells not associated with the first word line;
- applying the first fraction of the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line;
- and
- applying a second fraction of the programming voltage to a first bit line coupled to a second source/drain region of the selected memory cell through a diode and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line, wherein the other bit lines are coupled to the second source/drain regions of such non-selected memory cells through diodes.
2 more elements
A method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
- applying a first voltage to a plurality of word lines coupled to control gates of the memory cells, a plurality of program lines coupled to first source/drain regions of the memory cells and a plurality of bit lines coupled to second source/drain regions of the memory cells through diodes;
- reducing the first voltage applied to the plurality of word lines to a ground potential;
- increasing the voltage applied to a first word line coupled to the control gate of the selected memory cell from the ground potential to a first fraction of a programming voltage while leaving other word lines at the ground potential, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell;
- reducing the voltage applied to the plurality of program lines to the first fraction of the programming voltage;
- and
- applying a second fraction of the programming voltage to the plurality of bit lines.
3 more elements
A method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
- applying approximately ⅓ a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell;
- applying a ground potential to other word lines coupled to control gates of non-selected memory cells not associated with the first word line;
- applying approximately ⅓ the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line;
- and
- applying approximately ½ the programming voltage to a first bit line coupled to a second source/drain region of the selected memory cell through a diode and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line, wherein the other bit lines are coupled to the second source/drain regions of such non-selected memory cells through diodes.
2 more elements
A method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
- applying a ground potential to a plurality of word lines coupled to control gates of memory cells of the array;
- raising a first word line coupled to the control gate of the selected memory cell from the ground potential to a first fraction of a programming voltage, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell;
- holding other word lines coupled to control gates of non-selected memory cells not associated with the first word line at the ground potential while raising the first word line to the first fraction of the programming voltage;
- applying the first fraction of the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line;
- and
- applying a second fraction of the programming voltage to a first bit line coupled to a second source/drain region of the selected memory cell through a diode and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line, wherein the other bit lines are coupled to the second source/drain regions of such non-selected memory cells through diodes.
3 more elements
A method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
- applying a ground potential to a plurality of word lines coupled to control gates of memory cells of the array;
- raising a first word line coupled to the control gate of the selected memory cell from the ground potential to approximately ⅓ of a programming voltage, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell;
- holding other word lines coupled to control gates of non-selected memory cells not associated with the first word line at the ground potential while raising the first word line to approximately ⅓ of the programming voltage;
- applying approximately ⅓ the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line;
- and
- applying approximately ½ the programming voltage to a first bit line coupled to a second source/drain region of the selected memory cell through a diode and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line, wherein the other bit lines are coupled to the second source/drain regions of such non-selected memory cells through diodes.
3 more elements
Dependencies are inferred from the claim text.