MRAM architecture

A Magnetorestrictive Random Access Memory (MRAM), comprising:

• a first memory cell;
• a second memory cell coupled in parallel to said first memory cell, said second memory cell including a first Magnetic Tunnel Junction (MTJ) and excluding an isolation device;
• a programming line and a bit line adjacent to said second memory cell;
• and
• a third memory cell coupled in series to said first memory cell and said second memory cell.

A Magnetorestrictive Random Access Memory (MRAM) comprising:

• a first memory cell;
• a second memory cell coupled in parallel to said first memory cell, said second memory cell comprising a Magnetic Tunnel Junction (MTJ) and formed without an isolation device;
• and
• a programming line and a bit line adjacent to said second memory cell;
• and
• a third memory cell coupled in series to said first memory cell and said second memory cell.

A Magnetorestrictive Random Access Memory (MRAM) comprising:

• a plurality of bit lines;
• a first plurality of memory cells adjacent to a first bit line of said plurality of bit lines and each of said first plurality of memory cells consists of a Magnetic Tunnel Junction (MTJ);
• a plurality of programming lines, a first programming line of said plurality of programming lines adjacent to at least of said first plurality of memory cells;
• a second plurality of memory cells coupled in parallel with said plurality of memory cells, said second plurality of memory cells adjacent to a second bit line of said plurality of bit lines in each of said second plurality of cells consisting of an MTJ;
• a first memory cell and a second memory cell of said first plurality of memory cells are coupled in parallel to form a first memory cell group;
• and
• a third memory cell and a fourth memory cell of said first plurality of memory cells are coupled in parallel to form a second memory cell group,
• wherein said first memory cell group is coupled in series with said second memory cell group.

A Magnetorestrictive Random Access Memory (MRAM) comprising:

• a plurality of bit lines;
• a first plurality of memory cells adjacent to a first bit line of said plurality of bit lines and each of said first plurality of memory cells consists of a magnetic tunnel junction (MTJ);
• a plurality of programming lines, a first programming line of said plurality of programming lines adjacent to at least of said first plurality if memory cells;
• and
• a second plurality of memory cells coupled in series with said first plurality of memory cells, said second plurality of memory cells adjacent to a second bit line of said plurality of bit lines and each of said second plurality of cells consist of said MTJ.