Two-transistor SRAM cells
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.
Claims7
A two-transistor SRAM cell comprising:
- a first FET being an ultrathin FET of a first polarity type and including a gate, a source and a drain, the source being coupled to a first control line;
- a second FET being an ultrathin FET of a second polarity type and including a gate, a source and a drain, the source of the second FET being coupled to the gate of the first FET, the gate of the second FET being coupled to the drain of the first FET and the source of the second FET being coupled to a first potential;
- a first load device coupled between a second potential and the gate of the first FET;
- and
- a second load device coupled between the gate of the second FET and a second control line.
Dependencies are inferred from the claim text.