US 6,888,739 B2 · Nanocrystal write once read only memory for archival storage

Abstract

Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions. A gate insulator is formed opposing the channel region. The gate insulator includes a number of high work function nanoparticles. A gate is formed on the gate insulator. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the number of high work function nanoparticles in the gate insulator adjacent to the first source/drain region.

Claims43

Dependent claims

A write once read only memory cell, comprising:

a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET including:
a first source/drain region;
a second source/drain region;
a channel region between the first and the second source/drain regions;
a gate insulator formed opposing the channel region, wherein the gate insulator includes a number of high work function nanoparticles;
and
a gate formed on the gate insulator;
a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate;
a transmission line coupled to the second source/drain region;
and
wherein the MOSFET is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed MOSFET operates at reduced drain source current.

8 more elements

A memory array, comprising:

a number of write once read only memory cells, wherein each write once read only memory cell includes;
a first source/drain region;
a second source/drain region;
a channel region between the first and the second source/drain regions;
a gate insulator formed opposing the channel region, wherein the gate insulator includes a number of high work function nanoparticles, wherein the number of high work function nanoparticles include large work function nanocrystals selected from the group of p-type silicon germanium gates, p-type polycrystalline gate of silicon carbide, p-type polycrystalline gate of silicon oxycarbide, gallium nitride (GaN), and aluminum gallium nitride (AlGaN), wherein the nanocrystals are isolated from one another and not in conductive contact;
and
a gate formed on the gate insulator;
a number of bit lines coupled to the second source/drain region of each write once read only memory cell along rows of the memory array;
a number of word lines coupled to the gate of each write once read only memory cell along columns of the memory array;
an array plate, wherein the first source/drain region of each write once read only memory cell is coupled to the array plate by a conductive plug;
and
wherein at least one of write once read only memory cells is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed MOSFET operates at reduced drain source current.

9 more elements

A memory device, comprising:

a memory array, wherein the memory array includes a number of write once read only memory cells, wherein each write once read only memory cell includes;
a first source/drain region;
a second source/drain region;
a channel region between the first and the second source/drain regions;
a gate insulator formed opposing the channel region, wherein the gate insulator includes a number of high work function nanoparticles, wherein the number of high work function nanoparticles include heavily doped p-type polysilicon floating and isolated nanocrystals with a vacuum work function of 5.3 eV;
and
a gate formed on the gate insulator;
a number of bitlines coupled to the drain region of each write once read only memory cell along rows of the memory array;
a number of wordlines coupled to the gate of each write once read only memory cell along columns of the memory array;
an array plate, wherein the source region of each write once read only memory cell is coupled to the array plate by a conductive plug;
a wordline address decoder coupled to the number of wordlines;
a bitline address decoder coupled to the number of bitlines;
a sense amplifier coupled to the number of bitlines;
and
wherein at least one of the write once read only memory cells is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed MOSFET operates at reduced drain/source current.

12 more elements

An electronic system, comprising:

a processor;
and
a memory device coupled to the processor, wherein the memory device includes:
a memory array, wherein the memory array includes a number of write once read only memory cells, wherein each write once read only memory cell includes;
a first source/drain region;
a second source/drain region;
a channel region between the first and the second source/drain regions;
a gate insulator formed opposing the channel region, wherein the gate insulator includes a number of high work function nanoparticles, wherein the number of high work function nanoparticles include heavily doped p-type polysilicon floating and isolated nanocrystals with a vacuum work function of 5.3 eV;
and
a gate formed on the gate insulator;
a number of bitlines coupled to the drain region of each write once read only memory cell along rows of the memory array;
a number of wordlines coupled to the gate of each write once read only memory cell along columns of the memory array;
an array plate, wherein the source region of each write once read only memory cell is coupled to the array plate by a conductive plug;
a wordline address decoder coupled to the number of wordlines;
a bitline address decoder coupled to the number of bitlines;
a sense amplifier coupled to the number of bitlines;
and
wherein at least one of the write once read only memory cells is a programmed MOSFET having a charge trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed MOSFET operates at reduced drain/source current.

15 more elements

A method for operating a memory, comprising:

programming a charge into a number of high work function nanoparticles located in a gate insulator of one or more transistors in a DRAM array, wherein each transistor in the DRAM array includes a write once read only memory cell including;
a source region;
a drain region;
a channel region between the first and the second source/drain regions;
a gate insulator formed opposing the channel region, wherein the gate insulator includes a number of high work function nanoparticles;
and
a gate formed on the gate insulator;
a plug coupled to the source region, wherein the plug couples the source region to an array plate;
and
a transmission line coupled to the drain region;
wherein programming a charge into a number of high work function nanoparticles located in a gate insulator of the one or more transistors includes:
applying a first voltage potential to the source region of the transistor;
applying a second voltage potential to the drain region of the transistor;
and
applying a gate potential to a gate of the transistor;
and
wherein applying the first, second and control gate potentials to the one or more transistors includes creating a hot electron injection into the number of high work function nanoparticles located in a gate insulator of the one or more transistors adjacent to the source region such that the one or more transistors become programmed transistors and operate at reduced drain source current when operated in a forward direction.

14 more elements

A method for write once read only memory, comprising:

writing to one or more MOSFETs in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes:
a source region;
a drain region;
a channel region between the first and the second source/drain regions;
a gate insulator formed opposing the channel region, wherein the gate insulator includes a number of high work function nanoparticles;
a gate formed on the gate insulator;
a plug coupled to the source region, wherein the plug couples the source region to an array plate;
and
a transmission line coupled to the drain region;
wherein writing to the one or more MOSFETs in the reverse direction includes:
grounding the transmission line associated with an addressed MOSFET;
biasing the array plate to a voltage higher than VDD;
applying a gate potential to the gate of the addressed MOSFET creating a hot electron injection into the number of high work function nanoparticles in the gate insulator of the addressed MOSFET adjacent to the source region such that the addressed MOSFET becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction;
and
reading one or more MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes:
grounding the array plate;
precharging the bitline associated with an addressed MOSFET to a fractional voltage of VDD;
and
applying a gate potential of approximately 1.0 Volt to the gate of the addressed MOSFET.

16 more elements

A method for forming a write once read only memory cell, comprising:

forming a metal oxide semiconductor field effect transistor (MOSFET);
wherein forming the MOSFET includes:
forming a source region;
forming a drain region;
forming a channel region between the first and the second source/drain regions;
forming a gate insulator opposing the channel region, wherein forming the gate insulator includes forming a number of high work function nanoparticles in the gate insulator;
and
forming a gate on the gate insulator;
forming an array plate;
forming a conductive plug coupling the source region to the array plate;
and
forming a transmission line coupled to the drain region such that the write once read only memory cell can be programmed in a reverse direction to have a trapped charge in the number of high work function nanoparticles in the gate insulator adjacent to the source region by biasing the array plate to a voltage higher than VDD, grounding the transmission line, and selecting the gate by a wordline address, and wherein the programmed MOSFET will operate at reduced drain source current in a forward direction.

9 more elements

Dependencies are inferred from the claim text.

Nanocrystal write once read only memory for archival storage

Life of this patent

Nanocrystal write once read only memory for archival storage

Life of this patent

Abstract

Claims43