Methods of writing junction-isolated depletion mode ferroelectric memory devices
AssigneeMicron Technology, Inc.
InventorsCraig T. Salling, Brian W. Huber
Life of this patent
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Abstract
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
Claims6
A method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
- applying a ground potential to a first word line coupled to a control gate of the selected memory cell;
- applying a fraction of a programming voltage to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell;
- applying the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell through a diode;
- and
- applying the fraction of the programming voltage to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line, wherein the other bit lines are coupled to the second source/drain regions of such non-selected memory cells through diodes.
A method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
- applying a ground potential to a first word line coupled to a control gate of the selected memory cell;
- applying approximately ½ a programming voltage to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell;
- applying the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell through a diode;
- and
- applying approximately ½ the programming voltage to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
A method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
- applying a ground potential to a first word line coupled to a control gate of the selected memory cell;
- applying approximately 3V to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, wherein a gate/source voltage equal to approximately 6V is sufficient to cause a reversal of polarity of each memory cell;
- applying approximately 6V to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell through a diode;
- and
- applying approximately 3V to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
Dependencies are inferred from the claim text.