Content addressable memory cell
AssigneeMosaid Technologies Incorporated
InventorsRichard Foss, Charles Taylor, Curtis Richardson
Life of this patent
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Abstract
A content addressable memory (CAM) having a plurality of ternary memory cells, each ternary half cell comprising an equal number of transistors of a p-type and an n-type, the p-type transistors being formed in a first well region and the n-type transistors being formed in a second well region, the wells having at most one p+ to n+ region spacing, the transistors being interconnected to form the half ternary CAM cell and wherein the interconnections for the cell is restricted to a silicon layer and a first metal layer and connections between said cell and external signal lines is restricted to at least a second metal layer.
Claims7
A content addressable memory (CAM) cell having a plurality of 6T ternary memory cells in a fabricated semiconductor material, each half of the CAM cell comprising:
- an equal number of transistors of a p-type and an n-type, the p-type transistors being formed in a n-well region and the n-type transistors being formed in a p-well region of said semiconductor material, the p-wells being separated from the n-wells by at most one p+ to n+ region spacing, the transistors being interconnected to form said half CAM cell and wherein the interconnections between the half CAM cell are restricted to a first group of conductive layers and connections between said CAM cell and CAM signal lines external to said CAM cell are formed in a second group of conductive layers.
A content addressable memory (CAM), comprising:
- (a) a plurality of half ternary CAM cells each having at least one 6T ternary memory cell and an equal number of transistors of a p-type and an n-type, the p-type transistors being formed in a first well region and the n-type transistors being formed in a second well region of a semiconductor material, the first well region being separated from the second well region by at most one p+ to n+ region spacing, the transistors being interconnected to form said half ternary CAM cell and wherein the interconnections are restricted to a silicon layer and a first metal layer;
- (b) power lines formed in a second metal layer and coupled to said cells;
- (c) a plurality of search lines formed in a third metal layer;
- (d) a plurality of wordlines and match lines formed in a fourth metal layer;
- and
- (e) a plurality of bitlines formed in a fifth metal layer.
Dependencies are inferred from the claim text.