On-die de-coupling capacitor using bumps or bars
AssigneeIntel Corporation
InventorsRichard Scott List, Bruce A. Block, Mark T. Bohr
Life of this patent
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Abstract
A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.
Claims26
An apparatus comprising:
- a planarized metal interconnect line as the ultimate interconnect layer of an integrated circuit, the planarized metal interconnect line coupled to a bottom electrode of an electrically decoupling capacitor wherein a top electrode of the electrically decoupling capacitor is coupled to a flip chip bump contact such that the capacitor is disposed between and aligned between at least a portion of the metal interconnect line and the bump contact.
An apparatus comprising:
- an integrated circuit having a top metal layer interconnect as the ultimate interconnect layer of an integrated circuit, the top metal layer having a plurality of voltage bias lines with a plurality of voltage bias purposes;
- a decoupling capacitor coupled to a first top metal voltage bias line;
- a bump contact coupled to the decoupling capacitor and a second top metal voltage bias line such that the capacitor is disposed between and aligned between at least a portion of the first top metal voltage bias line and the bump contact, the second top metal voltage bias line having a different purpose than the first top metal voltage bias line coupled to the capacitor, wherein the bump contact provides power to the second metal voltage bias line and electrically decouples the first metal voltage bias line from the second metal voltage bias line.
An apparatus comprising:
- an integrated circuit having a layer of metal interconnect as the ultimate interconnect layer of the integrated circuit;
- a decoupling capacitor stack on the layer of metal interconnect;
- and
- a bump contact contacting the capacitor stack such that the capacitor stack is disposed between and aligned between at least a portion of the layer of metal and the bump contact.
An apparatus comprising:
- an integrated circuit comprising a layer of metal as the ultimate interconnect layer of the integrated circuit,
- a capacitor stack comprising:
- a blanket bottom electrode material on the layer of metal,
- a dielectric material having a dielectric constant greater than that of silicon dioxide on the blanket bottom electrode material,
- a blanket top electrode material on the dielectric material,
- a blanket passivation layer on the stack, and
- a bump contact contacting the top electrode material such that the top electrode material is disposed between and aligned between at least a portion of the layer of metal and the bump contact.
An apparatus comprising:
- an integrated circuit having a layer of metal interconnect as the ultimate interconnect layer of the integrated circuit, wherein the layer of metal comprises a first metal power bias voltage line and a second metal power bias voltage line;
- a decoupling capacitor stack on a portion of the first metal power bias voltage line, the decoupling capacitor having a characteristic to reduce a voltage droop on the first metal power bias voltage line;
- a passivation layer over a top and a side of the decoupling capacitor stack;
- a bump contact contacting the capacitor stack through a removed portion of the passivation layer over the top of the decoupling capacitor stack such that the capacitor stack is disposed between and aligned between at least a portion of the layer of metal and the bump contact, the bump contact also contacting the second metal power bias voltage line.
Dependencies are inferred from the claim text.