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US 6,888,483 B2Granted
High speed analog to digital converter
AssigneeBroadcom Corporation
InventorJan Mulder
Life of this patent
Estimating the term…
Abstract
An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1.
Claims27
An input stage comprising:
- a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array of amplifiers receives an input signal and a corresponding reference voltage at its inputs, and
- wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1;
- and
- a track-and-hold amplifier tracking the input signal with its output signal during clock phase φ1 and holding a sampled value during the clock phase φ2, the first autozero amplifier in each array receiving its input signal from the track-and-hold amplifier.
1 more element
An input stage comprising:
- a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array of amplifiers receives an input signal and a corresponding reference voltage at its inputs,
- wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ1 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1, and
- wherein, for each autozero amplifier, the circuit includes a plurality of transistors driven by either a supply voltage or the clock phase φ1.
An input stage comprising:
- a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array of amplifiers receives an input signal and a corresponding reference voltage at its inputs,
- wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1;
- and
- a transistor connected between the positive and negative differential outputs of the circuit, a gate of the transistor being driven by the clock phase φ1.
1 more element
An input stage comprising:
- a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array of amplifiers receives an input signal and a corresponding reference voltage at its inputs,
- wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1;
- and
- a transistor connected between the positive and negative differential inputs of the circuit, a gate of the transistor being driven by the clock phase φ1.
1 more element
An input stage comprising:
- a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array of amplifiers receives an input signal and a corresponding reference voltage at its inputs,
- wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1,
- wherein each of the autozero amplifiers includes a plurality of amplifier stages, and
- wherein the circuit is coupled to inputs of alternating stages.
1 more element
An input stage comprising:
- a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array of amplifiers receives an input signal and a corresponding reference voltage at its inputs,
- wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1;
- and
- an encoder converting outputs of the autozero amplifiers to an N-bit digital signal representing the input signal.
1 more element
An input stage comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2;
- a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal;
- and
- a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1,
- wherein, for each amplifier, the circuit comprises a plurality of transistors driven by either a supply voltage or the clock phase φ1.
2 more elements
An input stage comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1, and holding a sampled value during a clock phase φ2;
- a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal;
- and
- a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1,
- wherein, for each amplifier, the circuit comprises two cross-coupled transistors, two signal inputs and two signal outputs, the two signal outputs differentially connected to differential inputs of each corresponding amplifier, the two signal inputs differentially connected to the output signal of the track-and-hold amplifier.
2 more elements
An input stage comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2;
- a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal;
- and
- a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1,
- wherein the output signal comprises positive and negative differential outputs of the track-and-hold amplifier,
- wherein the circuit includes first, second, third and fourth transistors,
- wherein sources of the first and second transistors are connected to a positive differential output of the track-and-hold amplifier through a first sampling capacitor,
- wherein sources of the third and fourth transistors are connected to a negative differential output of the track-and-hold amplifier through a second sampling capacitor,
- wherein drains of the first and third transistors are connected to a positive differential input of the each amplifier,
- wherein drains of the second and fourth transistors are connected to a negative differential input of the each amplifier, and
- wherein gates of the second and third transistors are driven by the clock phase φ1.
8 more elements
An input stage comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2;
- a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal;
- a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1,
- wherein the output signal includes positive and negative differential outputs of the track-and-hold amplifier, and
- further comprising a transistor connected between the positive and negative differential outputs of the track and hold amplifier, a gate of the transistor being driven by the clock phase φ1.
2 more elements
An input stage comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2;
- a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal;
- and
- a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1,
- wherein a transfer function of the circuit for differential mode is HDM(φ1)=0, HDM(φ2)=1, and a transfer function for common mode is HCM(φ1)=1, HCM(φ2)=1.
2 more elements
An input stage comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2;
- a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal;
- and
- a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1,
- wherein each of the amplifiers comprises a plurality of amplifier stages, and
- wherein the circuit is coupled to an input of a first stage for each amplifier.
3 more elements
An input stage comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2;
- a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal;
- and
- a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1,
- wherein each of the amplifiers comprises a plurality of amplifier stages, and
- wherein the circuit is coupled to inputs of each stage.
3 more elements
An input stage comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2;
- a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal;
- and
- a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1;
- and
- a sampling capacitor at each input of the amplifiers for sampling the output of the track-and-hold amplifier.
3 more elements
An analog to digital converter comprising:
- a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2;
- a first plurality of amplifiers each inputting a signal corresponding to the output signal and a reference voltage;
- a switching circuit that receives the signal corresponding to the output signal and has a differential mode transfer function of approximately 1 on the clock phase φ2 and approximately 0 on the clock phase φ1;
- and
- a second plurality of amplifiers inputting the reference voltages and the signal corresponding to the output signal through the switching circuit, the reference voltages selected based on outputs of the first plurality of amplifiers.
2 more elements
An input stage comprising:
- a multi-phase clock;
- a track-and-hold amplifier tracking an input signal with its output signal during one phase of the multi-phase clock and holding a sampled value during another phase of the multi-phase clock;
- a first plurality of amplifiers each inputting a signal corresponding to the output signal and a reference voltage;
- switching means that receives the signal corresponding to the output signal and responsive to the multi-phase clock, the means substantially passing the signal corresponding to the output signal to a second plurality of amplifiers during the one phase and substantially rejecting the signal corresponding to the output signal during the another phase;
- and
- the second plurality of amplifiers inputting, through the switching means, the reference voltages and the output signal, the reference voltages selected based on outputs of the first plurality of amplifiers.
3 more elements
Dependencies are inferred from the claim text.