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AssigneeMatsushita Electric Industrial Co., Ltd.
InventorHiroyuki Yamauchi
Estimating the term…
In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors. Accordingly, the signal receiving circuit composed of the inverting circuit operates statically in response to the first and second pairs of differential signals.
A signal transmitting/receiving circuit comprising:
A signal transmitting/receiving circuit comprising:
A signal transmitting/receiving circuit comprising:
A signal transmitting/receiving circuit comprising:
A signal receiving circuit comprising a transistor,
A signal receiving method comprising
A signal receiving method comprising:
A signal receiving circuit
Dependencies are inferred from the claim text.