Controllable and testable oscillator apparatus for an integrated circuit
AssigneeThomson Licensing
InventorDavid Lawrence Albean
Life of this patent
Estimating the term…
Abstract
An integrated circuit (IC) includes an internal clock generator apparatus that provides various modes of operation of the integrated circuit. The internal clock generator apparatus includes a clock generator portion that is operable to provide a clock signal for various circuitry/logic of the integrated circuit and a control portion that is operable to receive a control signal to cause the integrated circuit to operate in one of several modes. In particular, the clock generator apparatus is responsive to the control signal, preferably from an external source, to bypass the clock signal, introduce a test clock signal for digital testing, and isolate and/or measure a delay through the clock generator portion of the clock generator apparatus.
Claims20
An integrated circuit comprising:
- an oscillator operable to generate a first clock signal comprising a delay logic providing a net inversion delay output signal and a divider in communication with the delay logic and operable to receive the net inversion delay output signal and produce the first clock signal;
- and
- control means responsive to a control signal from a source external to the integrated circuit and operable to cause the integrated circuit to operate in one of:
- a) a first mode of operation during which the integrated circuit operates in response to the first clock signal and produces a first output signal at an output terminal of the integrated circuit;
- and
- b) a second mode of operation during which the first clock signal is provided at the output terminal of the integrated circuit.
An integrated circuit comprising:
- an oscillator operable to generate a first clock signal at a first frequency having a net inversion delay output signal and a frequency divider responsive to the net inversion delay output signal and
- control means in communication with said oscillator and input pins of the integrated circuit, and responsive to a control signal applied to at least one of the input pins of the integrated circuit from a source external to the integrated circuit to cause the integrated circuit to operate in one of:
- a) a first mode of operation during which the oscillator is enabled for generating the first clock signal, and the first clock signal is provided only to circuitry internal to the integrated circuit, and the integrated circuit operates in response to the first clock signal for producing a first output signal at an output terminal of the integrated circuit;
- and
- b) a second mode of operation during which the oscillator is enabled for generating the first clock signal and the first clock signal is provided at the output terminal of the integrated circuit.
An integrated circuit comprising:
- a plurality of I/O pins;
- a clock generator in communication with at least one of the plurality of I/O pins and operable to generate a first clock signal of a first frequency;
- and
- control means in communication with the clock generator and at least some of the plurality of I/O pins, the control means responsive to a control signals from a source external to the integrated circuit, the control signal causing the control means to cause the integrated circuit to operate in one of:
- a) a first mode of operation during which the integrated operates in response to the first clock signal for producing a first output signal at one of the plurality of I/O pins;
- b) a second mode of operation during which the first clock signal is provided at an output pin of the plurality of I/O pins;
- c) a third mode of operation during which the first clock signal is provided at the output pin of the plurality of I/O pins and wherein circuitry internal to the integrated circuit operates in response to a second clock signal provided to the integrated circuit from a source external to the integrated circuit via one of the plurality of I/O pins;
- and
- d) a fourth mode of operation during which the clock generator is responsive to the second clock signal for providing an output signal at an output pin of the plurality of I/O pins for determining a delay associated with the clock generator.
Dependencies are inferred from the claim text.