Semiconductor integrated circuit device

A semiconductor integrated circuit device, comprising:

• a first circuit block to which a first supply voltage is to be applied, the first supply voltage being defined by first operating points;
• a first-stage intermediate circuit to which the first supply voltage is to be applied, and which receives an output of the first circuit block;
• a second-stage intermediate circuit to which a second supply voltage is to be applied, and receiving an output of the first-stage intermediate circuit, the second supply voltage being defined by second operating points;
• and
• a second circuit block to which the second supply voltage is to be applied and which receives an output of the second-stage intermediate circuit,
• wherein the second circuit block outputs a first-state first control signal to the second-stage intermediate circuit when the first supply voltage is applied to the first circuit block and the first-stage intermediate circuit so that the output of the second-stage intermediate circuit changes in state according to a change in the output of the first circuit block, and
• wherein the second circuit block outputs a second-state first control signal to the second-stage intermediate circuit when the first supply voltage is not applied to the first circuit block and the first-stage intermediate circuit so that the second-stage intermediate circuit controls its output to a potential of one of the second operating points, and further comprising:
• a second MOS transistor, the second supply voltage being applied to the second circuit block through the second MOS transistor;
• and
• a second controlling circuit which controls a state of the second MOS transistor,
• wherein the second controlling circuit outputs a first-state third control signal to the second-stage intermediate circuit when the second MOS transistor is to be in an ON state so that an input of the second-stage intermediate circuit is to be changed in state according to a change of the output of the second circuit block, and
• wherein the second controlling circuit outputs a second-state third control signal to the second-stage intermediate circuit when the second MOS transistor is to be in an OFF state so that the second-stage intermediate circuit controls its input to be at a potential of one of the second operating points.