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US 6,888,392 B2Granted
Method and related circuitry for buffering output signals of a chip with even number driving circuits
AssigneeVIA Technologies, Inc.
InventorsYi-Kuang Wei, Chia-Chun Huang, Chi-Ren Kuo
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Abstract
A method and related circuitry for driving output signals of a chip is disclosed. The method includes driving output signals with an even number of inverter driving circuits, and keeping an equivalent load of each inverter of the driving circuits substantially identical by keeping impedances of each driving circuit substantially identical.
Claims15
A method for correcting signals of a chip, the chip comprising:
- a first driving circuit including at least one first output end, each of the first output ends used for outputting a first driving signal;
- a second driving circuit including at least one second input end and at least one second output end, each of the second input ends connected to the corresponding first output end respectively, the second driving circuit generating a corresponding second driving signal according to the first driving signal and outputting the second driving signals from each of the second output ends;
- an output circuit including at least one driving end, each of the driving ends connected to the corresponding second output end respectively for receiving the second driving signal output from the second driving circuit;
- the method comprising:
- adding a load to at least one driving end of the output circuit to keep an impedance of each second input end that is in the second driving circuit and an impedance of each driving end that is in the output circuit substantially identical.
2 more elements
A chip comprising:
- an input circuit for providing an input signal;
- and
- a buffer circuit comprising:
- a first driving circuit connected to the input circuit including at least one first output end, the first driving circuit generating a corresponding first driving signal according to the input signal and outputting the first driving signal from each of the first output ends;
- and
- a second driving circuit including at least one second input end and at least one second output end, each of the second input ends connected to the corresponding first output end respectively, the second driving circuit generating a corresponding second driving signal according to the first driving signal and outputting the second driving signal from each of the second output ends;
- and
- an output circuit including at least one driving end, each of the driving ends connected to the corresponding second output end respectively, and including at least one load connected to one driving end for matching the impedance of that driving end with the impedances of the other driving ends, the output circuit for receiving the second driving signal;
- wherein an impedance of each second input end that is in the second driving circuit and an impedance of each driving end that is in the output circuit are substantially identical.
6 more elements
Dependencies are inferred from the claim text.