Clock generating circuit and clock generating method

A clock generating circuit, comprising:

• an oscillating circuit generating an original clock signal;
• a first measuring circuit that measures a first time period in which the original clock signal is at least a first threshold value;
• a second measuring circuit that measures a second time period in which the original clock signal is at most a second threshold value;
• a first control signal generating circuit that generates a first control signal having a first logic level in an initial state and transitions to a second logic level when the first time period is essentially equal to the second time period;
• and
• a synthesized clock generating circuit that provides a synthesized clock to another circuit not included in the clock generating circuit in accordance with the first control signal and the original clock signal.

A clock generating method, comprising the steps of:

• generating an original clock signal with an oscillation circuit;
• charging a charge node when the original clock signal reaches at least a predetermined magnitude;
• generating a control signal having a first logic level in an initial state that becomes a second logic level when the charge node reaches the predetermined potential;
• and
• providing a synthesized clock signal in response to the control signal and the original clock signal;
• and
• switching a power supply that is provided to the oscillation circuit in response to the control signal.

A clock generating method, comprising the steps of:

• generating an original clock signal with an oscillation circuit;
• measuring a first time period in which the original clock signal is at least a first threshold value;
• measuring a second time period in which the original clock signal is at most a second threshold value;
• generating a first control signal having a first logic level in an initial state and transitions to a second logic level when the first time period is essentially equal to the second time period;
• and
• providing a synthesized clock to another circuit not included in the clock generating circuit in accordance with the first control signal and the original clock signal.