Digital control variable delay circuit which is hardly susceptible to noise

A digital control variable delay circuit comprising:

• n amplitude control units which are connected in parallel and each of which receives a pair of input clock signals to be supplied to a differential pair and receives m-bit digital control signals, n and m each indicating a natural number of 2 or larger;
• and
• waveform shaping unit which is shared between the n amplitude control units and is connected, in common, to the outputs of the n amplitude control units, wherein
• the respective pairs of clock signals supplied to the n amplitude control units are shifted in phase by about 1/n period,
• each amplitude control unit being capable of varying the amplitude of each of the pair of clock signals into (m+1) values using the m-bit digital control signals, and outputting a pair of amplitude-varied clock signals,
• the waveform shaping unit receiving a pair of added clock signals obtained by adding and combining the pairs of amplitude-varied clock signals outputted from the n amplitude control units, shaping the waveform of each of the pair of added clock signals, and then outputting a pair of resultant clock signals as output signals.