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US 6,888,385 B2Granted
Phase locked loop (PLL) for integrated circuits
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsRajesh Bajaj, Nipun Padha
Life of this patent
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Abstract
An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree. “This enables the PLL to maintain the proper phase even during a sleep mode of operation.”
Claims22
An improved Phase Locked Loop (PLL) for a digital integrated circuit comprising:
- a routed clock tree connected between a VCO and a leaf cell,
- a frequency divider in a feedback path to a PFD input,
- wherein the VCO output is fedback through the feedback path to the PFD input, the feedback path including a clock tree replica coupled to the VCO output for providing a delay equal to the routed clock tree and the feedback path including the frequency divider coupled to the clock tree replica and directly coupled to the PFD input.
An improved Phase Locked Loop (PLL) for a digital integrated circuit comprising:
- a routed clock tree connected between a VCO and a leaf cell and a frequency divider in a feedback path to a PFD input, wherein
- the VCO output is fedback to the PFD input through a clock tree replica providing a delay equal to the routed clock tree, and
- wherein the routed clock tree is implemented by using a semi custom design approach where a netlist replicates the on-chip clock tree with the help of automatic placement, clock tree synthesis, and routing tools to achieve the desired delays.
A method for providing an improved Phase Locked Loop (PLL) for a digital integrated circuit, comprising:
- providing a Phase and Frequency Detector (PFD) for comparing an input clock and a generated clock,
- connecting a Voltage Controlled Oscillator (VCO) at an output of the PFD for producing a clock output,
- connecting a frequency divider in a feedback path to an input of the PFD that receives the generated clock, and
- wherein a VCO output is fedback through a clock tree replica providing a delay equal to a routed clock tree and then through the frequency divider to the input of the PFD that receives the generated clock, with the clock tree replica and the frequency divider forming the feedback path.
1 more element
A method for providing an improved Phase Locked Loop (PLL) for a digital integrated circuit, comprising:
- providing a Phase and Frequency Detector (PFD) for comparing an input clock and a generated clock,
- connecting a Voltage Controlled Oscillator (VCO) at an output of the PFD for producing a clock output,
- connecting a frequency divider in a feedback path to an input of the PFD that receives the generated clock,
- wherein a VCO output is feedback through a clock tree replica providing a delay equal to a routed clock tree and through the frequency divider to the input of the PFD that receives the generated clock, with the clock tree replica and the frequency divider forming the feedback path, and
- wherein the routed clock tree is implemented by using a semi custom design approach in which a netlist replicates the on-chip clock tree with the help of automatic placement, clock tree synthesis, and routing tools to achieve the desired delays.
2 more elements
A phase-locked loop, comprising:
- a phase detector operable to generate an error signal that is related to a phase difference between a reference signal and a delayed output signal;
- a signal-controlled oscillator coupled to the phase detector and operable to generate an output signal having a frequency that is related to the error signal;
- and
- a feedback circuit coupled to the phase detector and to the oscillator and operable to generate the delayed output signal by first delaying the output signal from the oscillator by a delay time that is substantially equal to a delay time that the output signal is delayed in propagating from the oscillator to a remote circuit node and by thereafter dividing the frequency of the output signal that has been delayed by the delay time that is substantially equal to the delay time that the output signal is delayed in propagating from the oscillator to a remote circuit node.
1 more element
An integrated circuit, comprising:
- a circuit;
- a delay path having an output node coupled to the circuit, an input node, and a signal delay;
- and
- a phase-locked loop having an output node coupled to the input node of the delay path, the phase-locked loop comprising,
- a phase detector operable to generate an error signal that is related to a phase difference between a reference signal and a delayed output signal,
- a signal-controlled oscillator coupled to the phase detector and operable to generate on the output node of the oscillator an output signal having a frequency that is related to the error signal, and
- a feedback circuit coupled to the phase detector and to the oscillator and operable to generate the delayed output signal by first delaying the output signal from the oscillator by the signal delay to generate a model output signal and by thereafter dividing a frequency of the model output signal.
4 more elements
An electronic system, comprising:
- an integrated circuit, comprising,
- a circuit,
- a delay path having an output node coupled to the circuit, an input node, and a signal delay, and
- a phase-locked loop having an output node coupled to the input node of the delay path, the phase-locked loop comprising,
- a phase detector operable to generate an error signal that is related to a phase difference between a reference signal and a delayed output signal,
- a signal-controlled oscillator coupled to the phase detector and operable to generate on the output node of the oscillator an output signal having a frequency that is related to the error signal, and
- a feedback circuit coupled to the phase detector and to the oscillator and operable to generate the delayed output signal by first delaying the output signal from the oscillator by the signal delay to generate a model output signal and by thereafter dividing a frequency of the model output signal.
4 more elements
A method of controlling a phase-locked loop, comprising:
- generating an error signal that is related to a phase difference between a reference signal and a delayed output signal;
- generating an output signal having a frequency that is related to the error signal;
- and
- generating the delayed output signal by delaying the output signal substantially by a same delay time that the output signal is delayed along a path to a circuit that receives the output signal and thereafter dividing the frequency of this signal.
1 more element
A method of controlling a phase-locked loop, comprising:
- designing a circuit having a delay;
- and
- replicating the delay of the circuit;
- delaying an output signal applied to the circuit by the replicated delay to generate a model delayed signal;
- after generating the model delayed signal, dividing a frequency of the model delayed signal to generate an adjusted output signal;
- adjusting a frequency of an output signal applied to the circuit as a function of the phase difference between the adjusted output signal and an input signal.
3 more elements
Dependencies are inferred from the claim text.