US 6,888,380 B2Granted

Latch circuit for latching a pair of complementary data signals

AssigneeNEC Electronics Corporation

InventorYasushi Aoki

Life of this patent

Estimating the term…

Abstract

A latch circuit includes a sample section for responding to complementary clock signals to sample complementary data signals during a sample period, a latch section for latching the sampled complementary data signals on latch output nodes to transfer the same through latch output nodes during a hold period, and a precharge section for precharging the latch output nodes during the sample period. The latch circuit has a smaller dead zone including a smaller setup time and a smaller hold time.

Claims7

Dependent claims

A latch circuit comprising:

a sample section activated during a sample period by a sample signal to sample a pair of complementary data signals, to deliver said complementary data signals through a pair of sample output nodes;
a latch section activated during a hold period by a hold signal to latch said complementary data signals through said sample output nodes, to deliver said complementary data signals through a pair of latch output nodes, said sample signal and said hold signal occurring alternately with each other;
and
a precharge section for precharging said latch output nodes during said sample period, wherein:
said latch section includes first and second inverters for receiving said complementary data signals through said sample output nodes, and a latch-section activating circuit for activating said first and second inverters during said hold period;
said first inverter includes a first transistor having a gate connected to one of said sample output nodes and connected between a high-potential power source line and one of said latch output nodes, a second transistor connected between said one of said latch output nodes and the other of said sample output nodes and being OFF during said sample period, and a third transistor having a gate connected to the other of said latch output nodes and connected between said other of said sample output nodes and a low-potential power source line;
and
said second inverter includes a fourth transistor having a gate connected to said other of said sample output nodes and connected between said high-potential power source line and said other of said latch output nodes, a fifth transistor connected between said other of said latch output nodes and said one of said sample output nodes and being OFF during said sample period, and a sixth transistor having a gate connected to said one of said latch output nodes and connected between said one of said sample output nodes and said low-potential power source line.

5 more elements

Dependencies are inferred from the claim text.

patentgrep

Loading patent…

Abstract

A latch circuit comprising:

a sample section activated during a sample period by a sample signal to sample a pair of complementary data signals, to deliver said complementary data signals through a pair of sample output nodes;
a latch section activated during a hold period by a hold signal to latch said complementary data signals through said sample output nodes, to deliver said complementary data signals through a pair of latch output nodes, said sample signal and said hold signal occurring alternately with each other;
and
a precharge section for precharging said latch output nodes during said sample period, wherein:
said latch section includes first and second inverters for receiving said complementary data signals through said sample output nodes, and a latch-section activating circuit for activating said first and second inverters during said hold period;
said first inverter includes a first transistor having a gate connected to one of said sample output nodes and connected between a high-potential power source line and one of said latch output nodes, a second transistor connected between said one of said latch output nodes and the other of said sample output nodes and being OFF during said sample period, and a third transistor having a gate connected to the other of said latch output nodes and connected between said other of said sample output nodes and a low-potential power source line;
and
said second inverter includes a fourth transistor having a gate connected to said other of said sample output nodes and connected between said high-potential power source line and said other of said latch output nodes, a fifth transistor connected between said other of said latch output nodes and said one of said sample output nodes and being OFF during said sample period, and a sixth transistor having a gate connected to said one of said latch output nodes and connected between said one of said sample output nodes and said low-potential power source line.

5 more elements