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US 6,888,377 B2Granted
Duo-mode keeper circuit
AssigneeInternational Business Machines Corporation
InventorHung C. Ngo
Life of this patent
Estimating the term…
Abstract
LSDL logic is provided with circuitry that has logic controls to provide two modes of operation. The half latch and the PFET that normally forms the keeper function on the dynamic node are modified. The inverter function of the series connected PFET and NFET have their corresponding positive and negative power supply terminals coupled to logic gates. In this way, the inverter may be turned ON so that the half latch functions as a keeper or it may be turned OFF to remove it from operating at all in the mode where the LSDL logic circuit needs to operate with a fast pulse clock. Likewise, the positive supply voltage may be removed while allowing the NFET device to operate to turn ON the PFET pull-up device for burn-in operation.
Claims21
A limited switch dynamic logic circuit comprising:
- a dynamic node;
- precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal;
- a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal;
- static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output;
- and
- a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper output reinforces a first logic state of said dynamic node and does not reinforce a second logic state of said dynamic node in response to logic states of said first and second supply signals.
3 more elements
A logic device comprising:
- a plurality of limited switch dynamic logic (LSDL) circuits wherein each of said LSDL circuits has a dynamic node, precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal, a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal, static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output, and a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper output reinforces a first logic state of said dynamic node and does not reinforce a second logic state of said dynamic node in response to logic states of said first and second supply signals.
A data processing system comprising:
- a central processing unit (CPU);
- and
- a memory operable for communicating instructions and operand data to said CPU, wherein said CPU includes a logic system having a logic device, said logic device including a plurality of limited switch dynamic logic (LSDL) circuits wherein each of said LSDL circuits has a dynamic node, precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal, a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal, static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output, and a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper output reinforces a first logic state of said dynamic node and does not reinforce a second logic state of said dynamic node in response to logic states of said first and second supply signals.
A limited switch dynamic logic circuit comprising:
- a dynamic node;
- precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal;
- a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal;
- static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output;
- and
- a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper circuit is selectively enabled during a burn-in mode and a slow clock mode by logic states of said first and second supply signals.
3 more elements
Dependencies are inferred from the claim text.