Programmable logic device with soft multiplier

A programmable logic device comprising:

• a multi-port RAM block which includes a first port including first address registers and first data register and which includes a second port including second address registers and second data registers;
• at least one look-up table stored in the RAM block;
• wherein respective storage locations of the at least one look up table are encoded with respective values representing respective products of respective multiplications of respective address values that address the respective storage locations and at least one other factor value;
• first programmable logic circuitry programmed to operate as a shift register which includes multiple tap outputs coupled to the first address registers;
• second programmable logic circuitry programmed to operate as multiply and accumulate circuitry which includes a multi-bit input coupled to the first data registers and includes an accumulator output;
• and
• address control circuitry that regulates access to the at least one look up tables by,
• providing read access to one storage location of the at least one look up table via the first address registers and the first data registers of the first port while concurrently providing write access to another storage location of the at least one look up table via the second address registers and the second data registers of the second port.

A programmable logic device comprising:

• a multi-port RAM block which includes a first port including first address registers and first data registers and which includes a second port including second address registers and second data registers;
• a first look up table stored in the RAM block;
• a second look up table stored in the RAM block;
• wherein respective storage locations of at least one or the other of the first look up table or the second look up table is encoded with respective values representing respective products of respective multiplications of respective address values that address the respective storage locations and at least one other factor value;
• first programmable logic circuitry programmed to operate as a shift register which includes multiple tap outputs coupled to the first address register;
• second programmable logic circuitry programmed to operate as multiply and accumulate circuitry which includes a multi-bit input coupled to the first data registers and includes an accumulator output;
• and
• address control circuitry that regulates access to the first and second look up tables by alternately,
• providing read access to the first table via the first address registers and the first data registers of the first port while concurrently providing write access to the second table via the second address registers and the second data registers of the second port, and
• providing read access to the second table via the first address registers and the first data registers of the first port while concurrently providing write access to the first table via the second address registers and the second data registers of the second port.

A programmable logic device comprising:

• a first multi-port RAM block which includes a first port including first address registers and first data registers and which includes a second port including second address registers and second data registers;
• at least one look-up table stored in the first RAM block;
• a second multi-port RAM block which includes a first port including first address registers and first data registers and which includes a second port including second address registers and a second data registers;
• at least one look-up table stored in the second RAM block;
• first programmable logic circuitry programmed to operate as a shift register which includes first multiple tap outputs coupled to multiple first address registers of the first port of the first RAM block and which includes second multiple tap outputs coupled to multiple first address registers of the first port of the second RAM block;
• second programmable logic circuitry programmed to operate as accumulate circuitry which includes a multi-bit input coupled to multiple first data registers of the first port and to multiple first data registers of the second port.

A method using a programmable logic device including a multi-port RAM block which includes a first port including first address registers and first data registers and which includes a second port including second address registers and a second data registers;

• first programmable logic circuitry programmed to operate as a shift register which includes multiple tap outputs coupled to multiple first address registers;
• and second programmable logic circuitry programmed to operate as multiply and accumulate circuitry which includes a multi-bit input coupled to multiple first data registers and includes an accumulator output, the method comprising:
• providing at least one look up table in the RAM block;
• and
• providing read access to one storage location of the at least one look up table via the first address registers and the first data registers of the first port while concurrently providing write access to another storage location of the at least one look up table via the second address registers and the second data registers of the second port.

A method using a programmable logic device including a multi-port RAM block which includes a first port including first address registers and first data registers and which includes a second port including second address registers and second data registers;

• first programmable logic circuitry programmed to operate as a shift register which includes multiple tap outputs coupled to the first address registers;
• and second programmable logic circuitry programmed to operate as multiply and accumulate circuitry which includes a multi-bit input coupled to the first data registers and includes an accumulator output, a method comprising:
• providing a first look up table and a second look up table in the RAM block;
• and
• regulating access to the first and second look up tables by alternately,
• providing read access to the first table via the first address registers and the first data registers of the first port while concurrently providing write access to the second table via the second address registers and the second data registers of the second port, and
• providing read access to the second table via the first address registers and the first data registers of the first port while concurrently providing write access to the first table via the second address registers and the second data registers of the second port.

A programmable logic device comprising:

• a multi-port RAM block which includes a first port including first address registers and first data registers and which includes a second port including second address registers and second data registers;
• wherein multiple registers of the first port are coupled to operate as a shift register which includes multiple tap outputs;
• wherein the multiple tap outputs are coupled to second multiple address registers of the second port;
• programmable logic circuitry programmed to operate as accumulate circuitry which includes a multi-bit input coupled to the second data registers and includes an accumulator output.