Programmable interface for field programmable gate array cores
AssigneeLeopard Logic, Inc.
InventorDale Wong
Life of this patent
Estimating the term…
Abstract
A programmable interface for FPGA cores embedded in an integrated circuit. The interface has an interconnect multiplexer (which includes demultiplexers) connected to the FPGA core and other elements of the integrated circuit. A control portion of the interface provides selection control bits to the interconnect multiplexer to make the desired connection configuration. Programmable latches in the control portion hold the selection bits which are loaded into the latches at the same time configuration bits are loaded into the integrated circuit to program the FPGA core. Alternatively, the control portion can be implemented by another FPGA core which is configured as a state machine to generate the selection control bits.
Claims24
In an integrated circuit having an embedded FPGA core, a programmable interface for said embedded FPGA core, said programmable interface comprising
- at least one multiplexer connected to said FPGA core and to a plurality of elements of said integrated circuit, said multiplexer selectably connecting said FPGA core to one of said elements;
- and
- a programmable control portion connected and providing selection bits to said one multiplexer so that reprogramming said control portion changes said multiplexer to connect said FPGA core to another of said plurality of elements.
For an integrated circuit having an embedded FPGA core, a programmable interface for said embedded FPGA core, said programmable interface connected to said FPGA core and to a plurality of elements of said integrated circuit, said programmable interface capable of selectably connecting said FPGA core to one of said elements in different connection configurations responsive to selection bits held in at least one programmable latch, a method of defining said different connection configurations comprising
- loading said selection bits into said at least one programmable latch in the same operation of loading configuration bits into said integrated circuit to program said FPGA core.
For an integrated circuit having a first embedded FPGA core, a programmable interface for said first embedded FPGA core, said programmable interface connected to said first FPGA core and to a plurality of elements of said integrated circuit, said programmable interface capable of selectably connecting said first FPGA core to one of said elements in different connection configurations responsive to selection bits from a second embedded FPGA core, a method of defining said different connection configurations comprising
- loading configuration bits into said integrated circuit to program said second embedded FPGA core in the same operation of loading configuration bits into said integrated circuit to program said first embedded FPGA core.
Dependencies are inferred from the claim text.