Programmable on-chip differential termination impedance
AssigneeAltera Corporation
InventorsBonnie I. Wang, Chiakang Sung, Khai Nguyen
Life of this patent
Estimating the term…
Abstract
The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.
Claims17
An integrated circuit comprising a differential impedance termination circuit, the differential impedance termination circuit comprising:
- first and second resistors;
- first and second transistors coupled in parallel, wherein drains of the first and second transistors are coupled to a first terminal of the first resistor, and sources of the first and second transistors are coupled to a first terminal of the second resistor;
- third and fourth transistors coupled in parallel, wherein drains of the third and fourth transistors are coupled to a second terminal of the first resistor, and sources of the third and fourth transistors are coupled to a second terminal of the second resistor;
- a third resistor having a first terminal coupled to the second terminal of the first resistor;
- and
- a fourth resistor having a first terminal coupled to the second terminal of the second resistor,
- the impedance termination circuit being coupled between first and second differential pins of the integrated circuit.
An integrated circuit comprising a differential termination circuit, the differential termination circuit comprising:
- first and second resistors coupled together in series;
- a first transistor having a drain coupled to a first terminal of the first resistor;
- a second transistor having a source coupled to the first terminal of the first resistor and a drain coupled to a second terminal of the first resistor and a first terminal of the second resistor;
- third and fourth resistors coupled together in series, the third resistor having a first terminal coupled to a source of the first transistor;
- and
- a third transistor having a drain coupled to the first terminal of the third resistor and a source coupled to a second terminal of the third resistor and a first terminal of the fourth resistor,
- the differential termination circuit being coupled between first and second differential pins of the integrated circuit.
An integrated circuit comprising a differential termination circuit that is coupled between first and second differential pins, the differential termination circuit comprising:
- first and second resistors;
- first and second transistors coupled in parallel, wherein drains of the first and second transistors are coupled to a first terminal of the first resistor, and sources of the first and second transistors are coupled to a first terminal of the second resistor;
- and
- third and fourth transistors coupled in parallel, wherein drains of the third and fourth transistors are coupled to a second terminal of the first resistor, and sources of the third
- wherein gates of the first, second, third, and fourth transistors are controlled by four independent control signals that control an impedance of the differential termination circuit.
Dependencies are inferred from the claim text.