Apparatus and method for testing a plurality of semiconductor chips

A semiconductor chip test system, comprising:

• a tester having n groups of data input/output pins of which each of the groups include k data input/output pins for inputting/outputting data through the plurality of data input/output pins;
• n groups of semiconductor chips, each group including m semiconductor chips, each semiconductor chip comprising k data input/output pads (or pins) to be tested by the tester;
• and
• a control means for sequentially outputting the data input from a first one to mth one of each of the n groups of semiconductor chips to the tester during a read operation and simultaneously supplying nk data output from the tester to the n groups of semiconductor chips during a write operation, wherein the control means, comprises:
• a clock signal generating means for generating a first clock signal in response to a rising edge of a clock signal input from the tester and generating a second clock signal in response to a falling edge of the clock signal input from the tester;
• a control signal generating means for generating a read command and a write command by inputting a command input from the tester;
• a read control signal generating means for sequentially generating m read control signals by inputting the read command in response to the second clock signal;
• a write control signal generating means for generating a write control signal in response to the write command;
• a read data control means for sequentially outputting the output data from a first semiconductor chip to the mth semiconductor chip of each of the n groups of semiconductor chips to the tester in response to the m read control signals;
• and
• a write data control means for simultaneously outputting the data input from the tester to the n groups of semiconductor chips in response to the write control signal.

A semiconductor test method for a semiconductor chip test system, the system including a tester having n groups of data input/output pins of which each of the groups include k data input/output pins for inputting/outputting data through the data input/output pins;

• and
• n groups of semiconductor chips being respectively including m semiconductor chips, and each of the m semiconductor chips comprising k data input/output pads (or pins) to be tested by the tester, comprising steps of:
• sequentially outputting the input data from a first semiconductor chip to mth semiconductor chip for each of the n groups of the semiconductor chips to the tester during a read operation;
• and
• simultaneously supplying nk data output from the tester to the n groups of semiconductor chips during a write operation, wherein the test method further comprises steps of:
• generating a first clock signal in response to a rising edge of a clock signal input from the tester, generating a second clock signal in response to a falling edge of the clock signal from the tester, and generating a read command and a write command by inputting a command input from the tester;
• generating sequentially m read control signals by inputting the read command in response to the second clock signal, and generating a write control signal in response to the write command;
• and
• outputting sequentially output data from the first semiconductor chip to the mth semiconductor chip for each of the n groups of semiconductor chips to the tester in response to each of the m read control signals during the read operation and simultaneously outputting the data input from the tester to the n groups of semiconductor chips in response to the write control signal during the write operation.