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US 6,888,365 B2Granted
Semiconductor wafer testing system
AssigneeInfineon Technologies North America Corp.
InventorsDaivid Suitwai Ma, James J. Dietz, George W. Alexander
Life of this patent
Estimating the term…
Abstract
A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.
Claims17
A semiconductor wafer testing system, comprising:
- a first buffer on a semiconductor wafer;
- a first plurality of dies;
- and
- a first test circuit connecting the first buffer to the first plurality of dies;
- where the first buffer writes test data onto a section of each die in the first plurality of dies through the first test circuit,
- where the first buffer reads the test data from the section of each die through the first test circuit, and
- where the first buffer writes additional test data onto another section of each die through the first test circuit, and where the first buffer reads the additional test data from the other section of each die through the first test circuit.
4 more elements
A semiconductor wafer testing system, comprising:
- a first buffer on a semiconductor wafer;
- a first plurality of dies;
- a first test circuit connecting the first buffer to the first plurality of dies;
- where the first buffer writes test data onto a section of each die in the first plurality of dies through the first test circuit,
- where the first test buffer reads the test data from the section of each die through the first test circuit,
- a second buffer on the semiconductor wafer;
- a second plurality of dies;
- a second test circuit connecting the second buffer to the second plurality of dies;
- where the second buffer writes second test data onto an area of each die in the second plurality of dies through the second test circuit,
- where the second buffer reads the second test date from the area of each die in the second plurality of dies through the second test circuit,
- where the second buffer writes additional second test data onto another area of each die in the second plurality of dies through the second test circuit, and
- where the second buffer reads the additional second test data from the other area of each die in the second plurality of dies through the second test circuit.
9 more elements
A semiconductor wafer testing system, comprising:
- a first die cluster connected to a first buffer through a first routing mechanism, where the first buffer is on a semiconductor wafer;
- a second die cluster connected to a second buffer through a second routing mechanism, where the second buffer is on the semiconductor wafer, wherein the dies within each cluster have the same configuration;
- and
- a wafer test pad connected to the first and second buffers through a bus;
- where the first and second buffers receive a first write signal from the wafer test pad,
- where the first buffer writes a first portion of the first write signal onto a first section of each die in the first die cluster at essentially the same time,
- where the second buffer writes a second portion of the first write signal onto a first area of each die in the second die cluster at essentially the same time,
- where the first buffer reads the first portion of the first write signal from the first section of each die in the first die cluster, and
- where the second buffer reads the second portion of the first write signal from the first area of each die in the second die cluster.
6 more elements
A semiconductor wafer testing system, comprising:
- a first die cluster connected to a first buffer through a first routing mechanism, where the first buffer is on a semiconductor wafer;
- a second die cluster connected to a second buffer through a second routing mechanism, where the second buffer is on the semiconductor wafer;
- and
- a wafer test pad connected to the first and second buffers through a bus;
- where the first and second buffers receive a first write signal from the wafer test pad,
- where the first buffer writes a first portion of the first write signal onto a first section of each die in the first die cluster,
- where the second buffer writes a second portion of the first write signal onto a first area of each die in the second die cluster,
- where the first buffer reads the first portion of the first write signal from the first section of each die in the first die cluster, and
- where the second buffer reads the second portion of the first write signal from the first area of each die in the second die cluster;
- where the first and second buffers receive a second write signal from the wafer test pad,
- where the first buffer writes a first portion of the second write signal onto a second section of each die in the first die cluster,
- where the second buffer writes a second portion of the second write signal onto a second area of each die in the second die cluster,
- where the first buffer reads the first portion of the second write signal from the second section of each die in the first die cluster, and
- where the second buffer reads the second portion of the second write signal for the second area of each die in the second die cluster.
11 more elements
Dependencies are inferred from the claim text.