Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device

A semiconductor device comprising:

• a semiconductor chip,
• a porous stress relaxing layer provided on a plane, whereon circuits and electrodes of said semiconductor chip are formed, of said semiconductor chip,
• a circuit layer provided on said stress relaxing layer,
• via-holes provided between the electrodes on said semiconductor chip and said circuit layer,
• conductive portions for connecting electrically said circuit layer and said electrodes in said via-holes,
• external terminals provided at designated portions on said circuits in a grid array pattern, and
• an organic protecting film provided on the plane opposite to the plane where the circuits and electrodes of said semiconductor chip are formed, wherein
• said porous stress relaxing layer has a greater porosity than that of the organic protecting film, and
• respective side planes of said stress relaxing layer, said semiconductor chip, and said organic protecting film are exposed to outside of the semiconductor device on a same plane.

A semiconductor device comprising:

• a semiconductor chip,
• a porous stress relaxing layer provided on a plane, whereon circuits and electrodes of said semiconductor chip are formed, of said semiconductor chip,
• a circuit layer provided on said stress relaxing layer,
• anisotropic conductive material for connecting electrically said circuit layer and said electrodes on said semiconductor chip,
• external terminals provided at designated portions on said circuits in a grid array pattern, and
• an organic protecting film provided on the plane opposite to the plane, where the circuits and electrodes of said semiconductor chip are formed, wherein
• said porous stress relaxing layer has a greater porosity than that of the organic protecting film, and
• respective side planes of said stress relaxing layer, said semiconductor chip, and said organic protecting film are exposed to outside of said semiconductor device on a same plane.

A semiconductor wafer comprising:

• a chip for forming a semiconductor device, having a plurality of chip areas comprising circuits and electrodes, respectively,
• a porous stress relaxing layer provided on a plane of said chip, whereon the circuits and the electrodes are formed,
• a circuit layer provided on said stress relaxing layer, and connected to said electrodes, and
• external terminals provided on said circuit layer, wherein
• an organic protecting film is provided on the plane opposite to the plane, whereon said porous stress relaxing layer is provided, of said chip,
• said porous stress relaxing layer has a greater porosity than that of the organic protecting film, and
• side planes of the stress relaxing layer are exposed to outside of the semiconductor device.

A semiconductor wafer comprising:

• a chip for forming a semiconductor device, having a plurality of chip areas comprising circuits and electrodes, respectively,
• a porous stress relaxing layer provided on a plane of said chip, whereon the circuits and the electrodes of said chip area are formed,
• a circuit layer provided on said stress relaxing layer,
• via-holes provided between said electrodes and said circuit layer,
• conductive portions for electrically connecting said circuit layer and said electrodes in said via-holes,
• external terminals provided at designated portions on said circuits in a grid array pattern, and
• an organic protecting film provided on the plane, opposite to the stress relaxing layer, of said chip,
• wherein said porous stress relaxing layer has a greater porosity than that of the organic protecting film, and
• wherein side planes of the stress relaxing layer are exposed to outside of the semiconductor device.

A semiconductor wafer comprising:

• a chip for forming a semiconductor device, having a plurality of chip areas comprising circuits and electrodes, respectively,
• a porous stress relaxing layer provided on a plane of said chip, whereon the circuits and the electrodes of said chip area are formed,
• a circuit layer provided on said stress relaxing layer,
• anisotropic conductive material for connecting electrically electrodes on a chip and a circuit layer,
• external terminals provided at designated portions on said circuits in a grid array pattern, and
• an organic protecting film provided on the plane opposite to the plane, whereon said circuits and electrodes are formed, of said chip,
• wherein said porous stress relaxing layer has a greater porosity than that of the organic protecting film, and
• wherein side planes of the stress relaxing layer are exposed to outside of the semiconductor device.