Lead frame chip scale package

An integrated circuit package for accommodating a semiconductor die, comprising:

• a planar lead frame comprising (a) a die attach pad supporting said semiconductor die on an upper surface of said die attach pad, and (b) substantially planar conductive leads positioned around an outer periphery of said die attach pad, wherein each of said conductive leads has a lower surface that is substantially coplanar with said lower surface of said die attach pad, said upper and lower surfaces of said die attach pad being located on opposite sides of said die attach pad;
• a plurality of bond wires each coupling one of said conductive leads to a corresponding bonding pad on said semiconductor die;
• and
• a plastic encapsulation enclosing said semiconductor die, said bond wires and said lead frame, exposing at a lower surface of said plastic encapsulation said lower surface of said die attach pad and said lower surfaces of said conductive leads;
• and
• an adhesive pad removably attached to said integrated circuit package, covering said lower surface of said die attach pad and said lower surfaces of said conductive leads, and
• wherein said integrated circuit package is one of a plurality of integrated circuit packages fabricated simultaneously on a lead frame panel that includes said lead frame, said lead frame panel comprising a two dimensional matrix array of devices areas wherein each device area includes a die attach pads and conductive leads that are positioned under the plastic encapsulation, and wherein said adhesive pad supports the array of die attach pads and conductive leads prior to singulation of the plurality of integrated circuit packages.

A lead frame panel suitable for use in packaging an array of integrated circuits, the lead frame panel being formed from a conductive sheet and having top and bottom surfaces, the lead frame panel comprising:

• a matrix of tie bars that extend in substantially perpendicular rows and columns to define a two dimensional array of immediately adjacent device areas separated only by the tie bars, each device area being suitable for use in an independent integrated circuit package;
• a multiplicity of die attach pads;
• and
• a multiplicity of conductive contacts, the conductive contacts being mechanically carried by the tie bars;
• and
• wherein each device area in the two dimensional array of immediately adjacent device areas includes one of the die attach pads and a plurality of the conductive contacts that are positioned generally adjacent the die attach pad.

A, panel assembly suitable for use in packaging a multiplicity of integrated circuits, the panel assembly having top and bottom surfaces and comprising:

• a lead frame panel formed from a conductive sheet, the lead frame panel being patterned to define at least one two dimensional array of adjacent device areas, each device area being suitable for use as part of an independent integrated circuit package and including a plurality of contacts;
• a plurality of dice, each die being associated with one of the device areas and being electrically connected to the associated contacts;
• and
• a molded cap that covers the two dimensional array of adjacent device areas while leaving bottom surfaces of the contacts exposed to facilitate electrical connection to external components, wherein encapsulation material that forms the molded cap is exposed at a bottom surface of the panel of integrated circuits to physically isolate the contacts;
• and
• an adhesive pad adhered to a bottom surface of the lead frame panel, whereby the adhesive pad serves to keep the encapsulation material exposed at the bottom of the panel assembly substantially co-planar with the bottom surfaces of the contacts and die attach pads.