One transistor SOI non-volatile random access memory cell

A semiconductor structure, comprising:

• a substrate;
• a buried insulator layer positioned over at least a portion of the substrate;
• a body region positioned over the buried insulator layer;
• a charge trapping region formed at an interface between the buried insulator layer and the body region;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A semiconductor structure, comprising:

• a substrate;
• a buried insulator layer positioned over at least a portion of the substrate;
• a body region positioned over the buried insulator layer;
• a charge trapping region formed in the body region near an interface between the buried insulator layer and the body region;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A semiconductor structure, comprising:

• a substrate;
• a buried insulator layer positioned over at least a portion of the substrate;
• a body region positioned over the buried insulator layer, the body region including a charge trapping oxynitride region, the oxynitride region having a refractive index within a range of approximately 1.75 to approximately 1.9;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A semiconductor structure, comprising:

• a substrate;
• a buried insulator layer positioned over at least a portion of the substrate;
• a body region positioned over the buried insulator layer, the body region including a charge trapping composite;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A semiconductor structure, comprising:

• a substrate;
• a buried insulator layer positioned over at least a portion of the substrate;
• a body region positioned over the buried insulator layer, the body region including a charge trapping laminate;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A memory cell, comprising:

• a substrate;
• a buried insulator layer formed on the substrate;
• and
• a transistor formed on the buried insulator layer, including:
• a floating body region, including a charge trapping region within the floating body region, the charge trapping region including silicon nitride (Si3N4);
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A memory cell, comprising:

• a substrate;
• a buried insulator layer formed on the substrate;
• and
• a transistor formed on the buried insulator layer, including:
• a floating body region, including a charge trapping region within the floating body region, the charge trapping region including an oxynitride;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A memory cell, comprising:

• a substrate;
• a buried insulator layer formed on the substrate;
• and
• a transistor formed on the buried insulator layer, including:
• a floating body region, including a charge trapping region within the floating body region, the charge trapping region including a metal oxide;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A memory cell, comprising:

• a substrate;
• a buried insulator layer formed on the substrate;
• and
• a transistor formed on the buried insulator layer, including:
• a floating body region, including a charge trapping region within the floating body region, the charge trapping region including a metal silicide;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A memory cell, comprising:

• a substrate;
• a buried insulator layer formed on the substrate;
• and
• a transistor formed on the buried insulator layer, including:
• a floating body region, including a charge trapping composite within the floating body region;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A memory cell, comprising:

• a substrate;
• a buried insulator layer formed on the substrate;
• and
• a transistor formed on the buried insulator layer, including:
• a floating body region, including a charge trapping laminate within the floating body region;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A memory cell, comprising:

• a substrate;
• a buried insulator layer formed on the substrate;
• and
• a transistor formed on the buried insulator layer, including:
• a floating body region having a number of sidewalls, the floating body region including a sidewall charge trapping region at or near at least a portion of at least one of the number of sidewalls;
• a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;
• a gate insulator layer formed over the channel region;
• and
• a gate formed over the gate insulator layer.

A method of forming a non-volatile memory cell, comprising:

• forming a body region over a buried oxide (BOX) insulator on a substrate;
• forming a charge trapping region in the body region;
• forming a first diffusion region and a second diffusion region to define a channel region in the body region;
• forming a gate dielectric over the channel region;
• and
• forming a gate over the gate dielectric.

A method of forming a non-volatile memory cell, comprising:

• forming a body region over a buried oxide (BOX) insulator on a substrate;
• forming a charge trapping silicon nitride (Si3N4) region in the body region;
• forming a first diffusion region and a second diffusion region to define a channel region in the body region;
• forming a gate dielectric over the channel region;
• and
• forming a gate over the gate dielectric.

A method of forming a non-volatile memory cell, comprising:

• forming a body region over a buried oxide (BOX) insulator on a substrate;
• forming a charge trapping oxynitride region in the body region;
• forming a first diffusion region and a second diffusion region to define a channel region in the body region;
• forming a gate dielectric over the channel region;
• and
• forming a gate over the gate dielectric.