High-density split-gate FinFET
AssigneeInternational Business Machines Corporation
InventorsEdward J. Nowak, BethAnn Rainey
Life of this patent
Estimating the term…
Abstract
Disclosed is a method and structure for forming a split-gate fin-type field effect transistor (FinFET). The invention produces a split-gate fin-type field effect transistor (FinFET) that has parallel fin structures. Each of the fin structures has a source region at one end, a drain region at the other end, and a channel region in the middle portion. Back gate conductors are positioned between channel regions of alternating pairs of the fin structures and front gate conductors are positioned between channel regions of opposite alternating pairs of the fin structures. Thus, the back gate conductors and the front gate conductors are alternatively interdigitated between channel regions of the fin structures.
Claims21
A split-gate fin-type field effect transistor (FinFET) comprising:
- a plurality of parallel fin structures;
- back gate conductors adjacent said fin structures;
- and
- front gate conductors adjacent said fin structures,
- wherein said back gate conductors and said front gate conductors are alternatively interdigitated between channel regions of said fin structures such that each of said channel regions has a back gate conductor on one side of each fin structure and a front gate conductor on the other side of said fin structure.
A split-gate fin-type field effect transistor (FinFET) comprising:
- a plurality of parallel fin structures;
- back gate conductors between channel regions of alternating pairs of said fin structures;
- front gate conductors between channel regions of opposite alternating pairs of said fin structures;
- a back gate wiring layer connected to said back gate conductors;
- a front gate wiring layer connected to said front gate conductors;
- a first insulator layer positioned between said front gate conductors and said back gate wiring layer;
- and
- a second insulator layer positioned between said back gate conductors and said front gate wiring layer.
A split-gate fin-type field effect transistor (FinFET) comprising:
- a plurality of parallel fin structures, wherein each of said fin structures comprises a source region in a first end of said fin, a drain region in a second end of said fin, and a channel region in a middle portion of said fin between said first end and said second end;
- back gate conductors between channel regions of alternating pairs of said fin structures;
- front gate conductors between channel regions of opposite alternating pairs of said fin structures, such that said back gate conductors and said front gate conductors are alternatively interdigitated between channel regions of said fin structures and such that each of said channel regions has a back gate conductor on one side of each fin structure and a front gate conductor on the other side of said fin structure;
- a well region positioned below said fin structures, wherein said well region is electrically connected to said back gate conductors;
- and
- a front gate wiring layer positioned above said fin structures, wherein said front gate wiring layer is electrically connected to said front gate conductors.
A split-gate fin-type field effect transistor (FinFET) comprising:
- a plurality of parallel fin structures, wherein each of said fin structures comprises a source region in a first end of said fin, a drain region in a second end of said fin, and a channel region in a middle portion of said fin between said first end and said second end;
- back gate conductors between channel regions of alternating pairs of said fin structures;
- front gate conductors between channel regions of opposite alternating pairs of said fin structures, such that said back gate conductors and said front gate conductors are alternatively interdigitated between channel regions of said fin structures and such that each of said channel regions has a back gate conductor on one side of each fin structure and a front gate conductor on the other side of said fin structure;
- a back gate wiring layer positioned below said fin structures wherein said back gate wiring layer is electrically connected to said back gate conductors;
- and
- a front gate wiring layer positioned above said fin structures, wherein said front gate wiring layer is electrically connected to said front gate conductors.
Dependencies are inferred from the claim text.