US 6,888,190 B2 · EEPROM with source line voltage stabilization mechanism

Abstract

A low-voltage nonvolatile memory array includes an N type semiconductor substrate having a memory region. A deep P well is formed in the semiconductor substrate. A cell N well is located within the memory region in the semiconductor substrate. The cell N well is situated above the deep ion well. A shallow P well serving as a buried bit line is doped within the cell ion well. The shallow P well is isolated by an STI layer, wherein the STI layer has a thickness greater than a well depth of the shallow ion well. At least one memory transistor with a stacked gate, a source, and a drain is formed on the shallow ion well. The source of the memory transistor is electrically coupled to the cell N well to induce a capacitor between the cell N well and the deep P well during a read operation, thereby avoiding read current bounce or potential power crash. A bit line overlies the memory transistor and is electrically connected to the drain of the memory transistor via a bit line contact plug short-circuiting the drain of the memory transistor and the shallow P well.

Claims15

Dependent claims

An electrically erasable programmable read only memory (EERPOM) with source line voltage stabilization mechanism, comprising:

a semiconductor substrate of a first conductivity type having a memory region;
a deep ion well of a second conductivity type formed in said semiconductor substrate;
a cell ion well of said first conductivity type located within said memory region in said semiconductor substrate, said cell ion well being situated above said deep ion well;
a shallow ion well of said second conductivity type serving as a buried bit line doped within said cell ion well, said shallow ion well being isolated by an STI layer, wherein said STI layer has a thickness greater than a well depth of said shallow ion well;
at least one memory transistor comprising a stacked gate, a source, and a drain formed on said shallow ion well, wherein said source of said memory transistor is electrically coupled to said cell ion well to induce a capacitor between said cell ion well and said deep ion well during a read operation, thereby avoiding read current bounce or potential power crash;
and
a bit line overlying said memory transistor and electrically connected to said drain of said memory transistor via a bit line contact plug short-circuiting said drain of said memory transistor and said shallow ion well.

4 more elements

An electrically erasable programmable read only memory (EERPOM) with source line voltage stabilization mechanism, comprising:

a semiconductor substrate of a first conductivity type having a memory region;
a deep ion well of a second conductivity typeformed in said semiconductor substrate;
a cell ion well of said first conductivity type located within said memory region in said semiconductor substrate, said cell ion well being situated above said deep ion well;
a shallow ion well of said second conductivity type serving as a buried bit line doped within said cell ion well, said shallow ion well being isolated by an STI layer,
wherein said STI layer has a thickness greater than a well depth of said shallow ion well;
at least one memory transistor comprising a stacked gate, a source, and a drain formed on said shallow ion well;
a selection transistor formed on said shallow ion well, said selection transistor has a first terminal serially connected to said source of said memory transistor, said selection transistor comprising a select gate and a second terminal electrically coupled to a source line, wherein said source line is electrically coupled to said cell ion well to induce a capacitor between said cell ion well and said deep ion well during a read operation, thereby avoiding read current bounce or potential power crash;
and
a bit line overlying said memory transistor and electrically connected to said drain of said memory transistor via a bit line contact plug short-circuiting said drain of said memory transistor and said shallow ion well.

6 more elements

An electrically erasable programmable read only memory (EERPOM) with source line voltage stabilization mechanism, comprising:

a semiconductor substrate of a first conductivity type having a memory region;
a deep ion well of a second conductivity type formed in said semiconductor substrate;
a cell ion well of said first conductivity type located within said memory region in said semiconductor substrate, said cell ion well being situated above said deep ion well;
a shallow ion well of said second conductivity type serving as a buried bit line doped within said cell ion well, said shallow ion well being isolated by an STI layer, wherein said STI layer has a thickness greater than a well depth of said shallow ion well;
at least one memory cell block comprising a plurality of serially connected memory cells formed on said shallow ion well;
a selection transistor formed on said shallow ion well at one end of said memory cell block, said selection transistor has a first terminal serially connected to said memory cell block, and said selection transistor comprising a select gate and a second terminal electrically coupled to a source line, wherein said source line is further electrically coupled to said cell ion well to induce a capacitor between said cell ion well and said deep ion well during a read operation, thereby avoiding read current bounce or potential power crash;
and
a bit line overlying said memory cell block and electrically connected to a drain of one of said plurality of serially connected memory cells at the other end of said memory cell block via a bit line contact plug short-circuiting said drain and said shallow ion well.

5 more elements

Dependencies are inferred from the claim text.

EEPROM with source line voltage stabilization mechanism

Life of this patent

EEPROM with source line voltage stabilization mechanism

Life of this patent

Abstract

Claims15