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US 6,888,185 B2Granted
Junction-isolated depletion mode ferroelectric memory devices
AssigneeMicron Technology, Inc.
InventorsCraig T. Salling, Brian W. Huber
Life of this patent
Estimating the term…
Abstract
Depletion mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
Claims19
A memory cell, comprising:
- a ferroelectric layer formed overlying a well region having a first conductivity type, wherein the well region is formed in a substrate having a second conductivity type opposite the first conductivity type;
- a control gate formed overlying the ferroelectric layer and coupled to a word line;
- a first source/drain region having the first conductivity type formed in the well region and coupled to a program line;
- a second source/drain region having the first conductivity type formed in the well region;
- a channel region having the first conductivity type formed in the well region and interposed between the first and second source/drain regions;
- and
- a diode interposed between the second source/drain region and a bit line.
4 more elements
A memory cell, comprising:
- a ferroelectric layer formed overlying and adjoining a well region having a first conductivity type, wherein the well region is formed in a substrate having a second conductivity type opposite the first conductivity type;
- a control gate formed overlying the ferroelectric layer and coupled to a word line;
- a first source/drain region having the first conductivity type formed in the well region and coupled to a program line;
- a second source/drain region having the first conductivity type formed in the well region;
- a channel region having the first conductivity type formed in the well region and interposed between the first and second source/drain regions;
- and
- a diode interposed between the second source/drain region and a bit line.
4 more elements
A memory cell, comprising:
- a gate dielectric layer formed overlying and adjoining a well region having a first conductivity type, wherein the well region is formed in a substrate having a second conductivity type opposite the first conductivity type;
- a ferroelectric layer formed overlying the gate dielectric layer;
- a control gate formed overlying the ferroelectric layer and coupled to a word line;
- a first source/drain region having the first conductivity type formed in the well region and coupled to a program line;
- a second source/drain region having the first conductivity type formed in the well region;
- a channel region having the first conductivity type formed in the well region and interposed between the first and second source/drain regions;
- and
- a diode interposed between the second source/drain region and a bit line.
5 more elements
A memory cell, comprising:
- a gate dielectric layer formed overlying and adjoining a well region having a first conductivity type, wherein the well region is formed in a substrate having a second conductivity type opposite the first conductivity type;
- a conductive floating gate formed overlying the gate dielectric layer;
- a ferroelectric layer formed overlying the conductive floating gate;
- a control gate formed overlying the ferroelectric layer and coupled to a word line;
- a first source/drain region having the first conductivity type formed in the well region and coupled to a program line;
- a second source/drain region having the first conductivity type formed in the well region;
- a channel region having the first conductivity type formed in the well region and interposed between the first and second source/drain regions;
- and
- a diode interposed between the second source/drain region and a bit line.
6 more elements
A memory cell, comprising:
- a ferroelectric layer formed overlying and adjoining a well region having a first conductivity type, wherein the well region is formed in a substrate having a second conductivity type opposite the first conductivity type;
- a control gate formed overlying the ferroelectric layer and coupled to a word line;
- a first source/drain region having the first conductivity type formed in the well region and coupled to a program line;
- a second source/drain region having the first conductivity type formed in the well region;
- a channel region having the first conductivity type formed in the well region and interposed between the first and second source/drain regions;
- and
- a diode formed as a second well region of the second conductivity type in the second source/drain region and coupled to a bit line.
4 more elements
A memory cell, comprising:
- a gate dielectric layer formed overlying a well region having a first conductivity type, wherein the well region is formed in a substrate having a second conductivity type opposite the first conductivity type;
- a conductive floating gate formed overlying the gate dielectric layer;
- a ferroelectric layer formed overlying the conductive floating gate;
- a control gate formed overlying the ferroelectric layer and coupled to a word line;
- a first source/drain region having the first conductivity type formed in the well region and coupled to a program line;
- a second source/drain region having the first conductivity type formed in the well region;
- a channel region having the first conductivity type formed in the well region and interposed between the first and second source/drain regions;
- and
- a diode formed as a second well region of the second conductivity type in the second source/drain region and coupled to a bit line.
6 more elements
Dependencies are inferred from the claim text.