Integrated circuit structure

#1. Technical Field

#The present invention relates generally to electronic packaging, and more particularly, to an organic semiconductor chip carrier and method of forming the same.

#2. Related Art

#Specific embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:

#FIG. 1 depicts a cross-sectional view of a related art semiconductor chip carrier;

#FIG. 2 depicts a top view of the related art semiconductor chip carrier;

#Although certain embodiments of the present invention will be shown and described in detail, it should be understood that various changes and modifications may be made without departing from the scope of the appended claims. The scope of the present invention will in no way be limited to the number of constituting components, the materials thereof, the shapes thereof, the relative arrangement thereof, etc., and are disclosed simply as an example of the embodiment. Although the drawings are intended to illustrate the present invention, the drawings are not necessarily drawn to scale.

#Referring to the drawings, FIG. 3 shows a substrate 100, including a ground plane 112, preferably comprising copper-Invar-copper (CIC). A first dielectric layer 114 is laminated to each side of the ground plane 112, using conventional lamination techniques. A pair of first controlled impedance signal planes 116 are formed, one over each of the first dielectric layers 114, using a conventional method known and used in the industry. The first signal planes 116 are preferably copper. A second dielectric layer 118 is formed over each of the first signal planes 116, using conventional lamination techniques. A pair of first power planes 120 are formed, one over each of the second dielectric layers 118, using conventional techniques. The first power planes 120 are preferably copper. A third dielectric layer 122 is laminated over each of the power planes 120. A pair of second controlled impedance signal planes 124 are formed, one over each of the third dielectric layers 122, using techniques similar to those used to form the first signal planes 116. The second signal planes 124 are preferably copper. A fourth dielectric layer 126 is laminated over each of the second signal planes 124, using conventional lamination techniques. In this example, the first, second, third and fourth dielectric layers 114, 118, 122, 126 comprise Rogers' 2300™ (Roger's Inc.). In particular, Rogers' 2300™ is a dielectric comprising a PTFE (polytetrafluroethylene) material filled with silicon particles. In the alternative, the first, second, third and fourth dielectric layers 114, 118, 122, 126 may be any other similar electronics laminate material, such as, epoxy resins, polyimide, polyphenylene ethers, etc.

#As shown in FIG. 4, a pair of second power planes 128 are laminated, one over each of the fourth dielectric layers 126 using conventional techniques. The surfaces of the second power planes 128 are etched to a thickness of approximately 2-9 microns, preferably using a fluid head etch process, to maintain a copper thickness suitable for laser drilling and electroplating an additional copper layer. It should be noted that the thickness of the second power planes 128, illustrated in the figures, is disproportionately large for the purpose of illustration only.